Getting Started with FPGA Programming with VHDL 收录时间:2018-02-26 15:50:41 文件大小:497MB 下载次数:384 最近下载:2021-01-22 05:48:18 磁力链接: magnet:?xt=urn:btih:191c5c556bef0da85989719225b59ca71fe30844 立即下载 复制链接 文件列表 07.Packages and Components/06.Demo - Packages and Components.mp4 46MB 08.Debugging and Analysis/02.Simulation with ModelSim.mp4 41MB 02.FPGA Technology Overview/04.A Look at the Development Board.mp4 38MB 06.Writing Concurrent Code/07.Demo - Resettable Timer.mp4 37MB 04.Introduction to VHDL/06.Interacting with Board IO.mp4 30MB 05.Writing Sequential Code/08.Demo - Sequential Constructs.mp4 30MB 02.FPGA Technology Overview/05.Setting up the EDA.mp4 20MB 08.Debugging and Analysis/03.SignalTap Logic Analyzer.mp4 19MB 02.FPGA Technology Overview/03.What Is an FPGA.mp4 16MB 04.Introduction to VHDL/04.Ports and Board IO.mp4 15MB 02.FPGA Technology Overview/06.Project Setup.mp4 13MB 02.FPGA Technology Overview/08.Programming the FPGA.mp4 10MB 02.FPGA Technology Overview/07.Pin Assignments and the Pin Planner.mp4 9MB 01.Course Overview/01.Course Overview.mp4 9MB 07.Packages and Components/02.The IEEE Library and Standard Logic.mp4 8MB 03.Digital Design Primer/04.Addition and Multiplication.mp4 8MB 05.Writing Sequential Code/05.More Data Types.mp4 7MB 07.Packages and Components/04.Components and Port Maps.mp4 7MB 03.Digital Design Primer/05.Flip-flop, MUX, and LUT.mp4 7MB 03.Digital Design Primer/03.Logic Gates.mp4 7MB 05.Writing Sequential Code/07.If, Case, and Loop Statements.mp4 7MB 06.Writing Concurrent Code/04.Conditional Signal Assignments.mp4 6MB 06.Writing Concurrent Code/05.Block Statement.mp4 6MB 07.Packages and Components/03.Packages and Libraries.mp4 6MB 06.Writing Concurrent Code/03.Concurrent Signal Assignments.mp4 6MB 05.Writing Sequential Code/06.Variables.mp4 6MB 05.Writing Sequential Code/03.Processes.mp4 5MB fpga-vhdl-programming-getting-started.zip 5MB 02.FPGA Technology Overview/01.Course Overview.mp4 4MB 03.Digital Design Primer/06.Clocks and Timing.mp4 4MB 04.Introduction to VHDL/02.VHDL.mp4 4MB 04.Introduction to VHDL/03.Entity and Architecture.mp4 4MB 06.Writing Concurrent Code/02.Delays.mp4 4MB 04.Introduction to VHDL/05.Bits and Bit Vectors.mp4 4MB 07.Packages and Components/05.Generate Statement.mp4 4MB 06.Writing Concurrent Code/01.Overview.mp4 4MB 05.Writing Sequential Code/04.Wait Statement.mp4 4MB 03.Digital Design Primer/02.Boolean Logic.mp4 3MB 08.Debugging and Analysis/05.Course Summary.mp4 3MB 05.Writing Sequential Code/01.Overview.mp4 3MB 05.Writing Sequential Code/02.Signals.mp4 3MB 06.Writing Concurrent Code/06.Clocks.mp4 3MB 06.Writing Concurrent Code/08.Summary.mp4 3MB 02.FPGA Technology Overview/09.Summary.mp4 2MB 03.Digital Design Primer/07.Logic Element.mp4 2MB 03.Digital Design Primer/08.Summary.mp4 2MB 07.Packages and Components/01.Overview.mp4 2MB 07.Packages and Components/07.Summary.mp4 2MB 08.Debugging and Analysis/04.Summary.mp4 2MB 04.Introduction to VHDL/01.Introduction.mp4 1MB 04.Introduction to VHDL/07.Summary.mp4 1MB 03.Digital Design Primer/01.Overview.mp4 1MB 02.FPGA Technology Overview/02.Module Overview.mp4 1MB 08.Debugging and Analysis/01.Overview.mp4 1MB 05.Writing Sequential Code/09.Summary.mp4 806KB 08.Debugging and Analysis/02.Simulation with ModelSim.srt 13KB 02.FPGA Technology Overview/03.What Is an FPGA.srt 13KB 07.Packages and Components/06.Demo - Packages and Components.srt 13KB 02.FPGA Technology Overview/05.Setting up the EDA.srt 11KB 06.Writing Concurrent Code/07.Demo - Resettable Timer.srt 10KB 05.Writing Sequential Code/08.Demo - Sequential Constructs.srt 10KB 08.Debugging and Analysis/03.SignalTap Logic Analyzer.srt 8KB 04.Introduction to VHDL/06.Interacting with Board IO.srt 8KB 04.Introduction to VHDL/04.Ports and Board IO.srt 8KB 02.FPGA Technology Overview/04.A Look at the Development Board.srt 7KB 03.Digital Design Primer/03.Logic Gates.srt 6KB 05.Writing Sequential Code/05.More Data Types.srt 6KB 07.Packages and Components/04.Components and Port Maps.srt 6KB 03.Digital Design Primer/04.Addition and Multiplication.srt 6KB 07.Packages and Components/02.The IEEE Library and Standard Logic.srt 5KB 05.Writing Sequential Code/07.If, Case, and Loop Statements.srt 5KB 06.Writing Concurrent Code/05.Block Statement.srt 5KB 06.Writing Concurrent Code/04.Conditional Signal Assignments.srt 5KB 05.Writing Sequential Code/06.Variables.srt 5KB 06.Writing Concurrent Code/03.Concurrent Signal Assignments.srt 5KB 03.Digital Design Primer/05.Flip-flop, MUX, and LUT.srt 5KB 07.Packages and Components/03.Packages and Libraries.srt 4KB 02.FPGA Technology Overview/06.Project Setup.srt 4KB 02.FPGA Technology Overview/01.Course Overview.srt 4KB 04.Introduction to VHDL/05.Bits and Bit Vectors.srt 4KB 05.Writing Sequential Code/03.Processes.srt 4KB 06.Writing Concurrent Code/01.Overview.srt 4KB 04.Introduction to VHDL/02.VHDL.srt 4KB 05.Writing Sequential Code/01.Overview.srt 3KB 06.Writing Concurrent Code/02.Delays.srt 3KB 05.Writing Sequential Code/04.Wait Statement.srt 3KB 04.Introduction to VHDL/03.Entity and Architecture.srt 3KB 07.Packages and Components/05.Generate Statement.srt 3KB 02.FPGA Technology Overview/08.Programming the FPGA.srt 3KB 05.Writing Sequential Code/02.Signals.srt 3KB 01.Course Overview/01.Course Overview.srt 3KB 03.Digital Design Primer/06.Clocks and Timing.srt 3KB 02.FPGA Technology Overview/07.Pin Assignments and the Pin Planner.srt 3KB 03.Digital Design Primer/02.Boolean Logic.srt 3KB 08.Debugging and Analysis/05.Course Summary.srt 2KB 06.Writing Concurrent Code/08.Summary.srt 2KB 07.Packages and Components/01.Overview.srt 2KB 06.Writing Concurrent Code/06.Clocks.srt 2KB 03.Digital Design Primer/07.Logic Element.srt 2KB 02.FPGA Technology Overview/09.Summary.srt 2KB 04.Introduction to VHDL/01.Introduction.srt 1KB 03.Digital Design Primer/01.Overview.srt 1KB 02.FPGA Technology Overview/02.Module Overview.srt 1KB 03.Digital Design Primer/08.Summary.srt 1KB 08.Debugging and Analysis/01.Overview.srt 1KB 08.Debugging and Analysis/04.Summary.srt 1KB 07.Packages and Components/07.Summary.srt 1KB 04.Introduction to VHDL/07.Summary.srt 995B 05.Writing Sequential Code/09.Summary.srt 649B