589689.xyz

ALDEC ACTIVE HDL

  • 收录时间:2018-03-19 13:39:46
  • 文件大小:470MB
  • 下载次数:12
  • 最近下载:2020-11-08 04:32:12
  • 磁力链接:
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文件列表

  1. data1.cab 146MB
  2. Service_Pack_1_SPK.exe 62MB
  3. SCH/Xilinx/data1.cab 56MB
  4. vhdl/ChipExpress/data1.cab 35MB
  5. vhdl/Actel/data1.cab 26MB
  6. vhdl/Xilinx/data1.cab 19MB
  7. vhdl/LatticeCPLD/data1.cab 17MB
  8. VERILOG/Xilinx/data1.cab 14MB
  9. vhdl/Altera/data1.cab 13MB
  10. vhdl/LatticeORCA/data1.cab 10MB
  11. VERILOG/Actel/data1.cab 8MB
  12. VERILOG/LatticeCPLD/data1.cab 7MB
  13. VERILOG/ChipExpress/data1.cab 6MB
  14. VERILOG/Altera/data1.cab 6MB
  15. jc/FarmMC.exe 5MB
  16. vhdl/Atmel/data1.cab 4MB
  17. VERILOG/LatticeORCA/data1.cab 4MB
  18. VERILOG/QuickL/data1.cab 2MB
  19. vhdl/QuickL/data1.cab 2MB
  20. VERILOG/Atmel/data1.cab 2MB
  21. vhdl/Triscend/data1.cab 2MB
  22. vhdl/Cypress/data1.cab 1MB
  23. VERILOG/Cypress/data1.cab 955KB
  24. VERILOG/Triscend/data1.cab 905KB
  25. SCH/Xilinx/data1.hdr 489KB
  26. data1.hdr 462KB
  27. SCH/Xilinx/_INST32I.EX_ 290KB
  28. VERILOG/Actel/_INST32I.EX_ 290KB
  29. VERILOG/Altera/_INST32I.EX_ 290KB
  30. VERILOG/Atmel/_INST32I.EX_ 290KB
  31. VERILOG/ChipExpress/_INST32I.EX_ 290KB
  32. VERILOG/Cypress/_INST32I.EX_ 290KB
  33. VERILOG/LatticeCPLD/_INST32I.EX_ 290KB
  34. VERILOG/LatticeORCA/_INST32I.EX_ 290KB
  35. VERILOG/QuickL/_INST32I.EX_ 290KB
  36. VERILOG/Triscend/_INST32I.EX_ 290KB
  37. VERILOG/Xilinx/_INST32I.EX_ 290KB
  38. vhdl/Actel/_INST32I.EX_ 290KB
  39. vhdl/Altera/_INST32I.EX_ 290KB
  40. vhdl/Atmel/_INST32I.EX_ 290KB
  41. vhdl/ChipExpress/_INST32I.EX_ 290KB
  42. vhdl/Cypress/_INST32I.EX_ 290KB
  43. vhdl/LatticeCPLD/_INST32I.EX_ 290KB
  44. vhdl/LatticeORCA/_INST32I.EX_ 290KB
  45. vhdl/QuickL/_INST32I.EX_ 290KB
  46. vhdl/Triscend/_INST32I.EX_ 290KB
  47. vhdl/Xilinx/_INST32I.EX_ 290KB
  48. setup.ins 224KB
  49. SCH/Xilinx/_sys1.cab 171KB
  50. VERILOG/Actel/_sys1.cab 171KB
  51. VERILOG/Altera/_sys1.cab 171KB
  52. VERILOG/Atmel/_sys1.cab 171KB
  53. VERILOG/ChipExpress/_sys1.cab 171KB
  54. VERILOG/Cypress/_sys1.cab 171KB
  55. VERILOG/LatticeCPLD/_sys1.cab 171KB
  56. VERILOG/LatticeORCA/_sys1.cab 171KB
  57. VERILOG/QuickL/_sys1.cab 171KB
  58. VERILOG/Triscend/_sys1.cab 171KB
  59. VERILOG/Xilinx/_sys1.cab 171KB
  60. vhdl/Actel/_sys1.cab 171KB
  61. vhdl/Altera/_sys1.cab 171KB
  62. vhdl/Atmel/_sys1.cab 171KB
  63. vhdl/ChipExpress/_sys1.cab 171KB
  64. vhdl/Cypress/_sys1.cab 171KB
  65. vhdl/LatticeCPLD/_sys1.cab 171KB
  66. vhdl/LatticeORCA/_sys1.cab 171KB
  67. vhdl/QuickL/_sys1.cab 171KB
  68. vhdl/Triscend/_sys1.cab 171KB
  69. vhdl/Xilinx/_sys1.cab 171KB
  70. Relnotes1.htm 161KB
  71. crack/RORAHDL62SP1.exe 145KB
  72. VERILOG/Xilinx/data1.hdr 145KB
  73. VERILOG/LatticeORCA/data1.hdr 131KB
  74. Relnotes.htm 117KB
  75. Appendix.htm 116KB
  76. SCH/Xilinx/Setup.exe 72KB
  77. VERILOG/Actel/Setup.exe 72KB
  78. VERILOG/Altera/Setup.exe 72KB
  79. VERILOG/Atmel/Setup.exe 72KB
  80. VERILOG/ChipExpress/Setup.exe 72KB
  81. VERILOG/Cypress/Setup.exe 72KB
  82. VERILOG/LatticeCPLD/Setup.exe 72KB
  83. VERILOG/LatticeORCA/Setup.exe 72KB
  84. VERILOG/QuickL/Setup.exe 72KB
  85. VERILOG/Triscend/Setup.exe 72KB
  86. VERILOG/Xilinx/Setup.exe 72KB
  87. vhdl/Actel/Setup.exe 72KB
  88. vhdl/Altera/Setup.exe 72KB
  89. vhdl/Atmel/Setup.exe 72KB
  90. vhdl/ChipExpress/Setup.exe 72KB
  91. vhdl/Cypress/Setup.exe 72KB
  92. vhdl/LatticeCPLD/Setup.exe 72KB
  93. vhdl/LatticeORCA/Setup.exe 72KB
  94. vhdl/QuickL/Setup.exe 72KB
  95. vhdl/Triscend/Setup.exe 72KB
  96. vhdl/Xilinx/Setup.exe 72KB
  97. Setup.exe 72KB
  98. VERILOG/ChipExpress/setup.ins 72KB
  99. VERILOG/LatticeCPLD/setup.ins 72KB
  100. VERILOG/LatticeORCA/setup.ins 72KB
  101. VERILOG/QuickL/setup.ins 71KB
  102. vhdl/ChipExpress/setup.ins 71KB
  103. vhdl/LatticeCPLD/setup.ins 71KB
  104. vhdl/LatticeORCA/setup.ins 71KB
  105. SCH/Xilinx/setup.ins 71KB
  106. VERILOG/Triscend/setup.ins 71KB
  107. VERILOG/Cypress/setup.ins 71KB
  108. vhdl/QuickL/setup.ins 71KB
  109. VERILOG/Altera/setup.ins 71KB
  110. VERILOG/Xilinx/setup.ins 71KB
  111. VERILOG/Actel/setup.ins 71KB
  112. VERILOG/Atmel/setup.ins 71KB
  113. vhdl/Triscend/setup.ins 71KB
  114. vhdl/Cypress/setup.ins 71KB
  115. vhdl/Altera/setup.ins 71KB
  116. vhdl/Xilinx/setup.ins 71KB
  117. vhdl/Actel/setup.ins 71KB
  118. vhdl/Atmel/setup.ins 71KB
  119. VERILOG/Atmel/data1.hdr 61KB
  120. Rel00009.gif 57KB
  121. crack/crack1.exe 52KB
  122. crack1.exe 52KB
  123. vhdl/Xilinx/data1.hdr 45KB
  124. Relnotoc.htm 40KB
  125. SCH/Xilinx/_Setup.dll 34KB
  126. VERILOG/Actel/_Setup.dll 34KB
  127. VERILOG/Altera/_Setup.dll 34KB
  128. VERILOG/Atmel/_Setup.dll 34KB
  129. VERILOG/ChipExpress/_Setup.dll 34KB
  130. VERILOG/Cypress/_Setup.dll 34KB
  131. VERILOG/LatticeCPLD/_Setup.dll 34KB
  132. VERILOG/LatticeORCA/_Setup.dll 34KB
  133. VERILOG/QuickL/_Setup.dll 34KB
  134. VERILOG/Triscend/_Setup.dll 34KB
  135. VERILOG/Xilinx/_Setup.dll 34KB
  136. vhdl/Actel/_Setup.dll 34KB
  137. vhdl/Altera/_Setup.dll 34KB
  138. vhdl/Atmel/_Setup.dll 34KB
  139. vhdl/ChipExpress/_Setup.dll 34KB
  140. vhdl/Cypress/_Setup.dll 34KB
  141. vhdl/LatticeCPLD/_Setup.dll 34KB
  142. vhdl/LatticeORCA/_Setup.dll 34KB
  143. vhdl/QuickL/_Setup.dll 34KB
  144. vhdl/Triscend/_Setup.dll 34KB
  145. vhdl/Xilinx/_Setup.dll 34KB
  146. VERILOG/LatticeCPLD/data1.hdr 30KB
  147. SCH/Xilinx/_ISDel.exe 27KB
  148. VERILOG/Actel/_ISDel.exe 27KB
  149. VERILOG/Altera/_ISDel.exe 27KB
  150. VERILOG/Atmel/_ISDel.exe 27KB
  151. VERILOG/ChipExpress/_ISDel.exe 27KB
  152. VERILOG/Cypress/_ISDel.exe 27KB
  153. VERILOG/LatticeCPLD/_ISDel.exe 27KB
  154. VERILOG/LatticeORCA/_ISDel.exe 27KB
  155. VERILOG/QuickL/_ISDel.exe 27KB
  156. VERILOG/Triscend/_ISDel.exe 27KB
  157. VERILOG/Xilinx/_ISDel.exe 27KB
  158. vhdl/Actel/_ISDel.exe 27KB
  159. vhdl/Altera/_ISDel.exe 27KB
  160. vhdl/Atmel/_ISDel.exe 27KB
  161. vhdl/ChipExpress/_ISDel.exe 27KB
  162. vhdl/Cypress/_ISDel.exe 27KB
  163. vhdl/LatticeCPLD/_ISDel.exe 27KB
  164. vhdl/LatticeORCA/_ISDel.exe 27KB
  165. vhdl/QuickL/_ISDel.exe 27KB
  166. vhdl/Triscend/_ISDel.exe 27KB
  167. vhdl/Xilinx/_ISDel.exe 27KB
  168. vhdl/Altera/data1.hdr 25KB
  169. SCH/Xilinx/lang.dat 23KB
  170. VERILOG/Actel/lang.dat 23KB
  171. VERILOG/Altera/lang.dat 23KB
  172. VERILOG/Atmel/lang.dat 23KB
  173. VERILOG/ChipExpress/lang.dat 23KB
  174. VERILOG/Cypress/lang.dat 23KB
  175. VERILOG/LatticeCPLD/lang.dat 23KB
  176. VERILOG/LatticeORCA/lang.dat 23KB
  177. VERILOG/QuickL/lang.dat 23KB
  178. VERILOG/Triscend/lang.dat 23KB
  179. VERILOG/Xilinx/lang.dat 23KB
  180. vhdl/Actel/lang.dat 23KB
  181. vhdl/Altera/lang.dat 23KB
  182. vhdl/Atmel/lang.dat 23KB
  183. vhdl/ChipExpress/lang.dat 23KB
  184. vhdl/Cypress/lang.dat 23KB
  185. vhdl/LatticeCPLD/lang.dat 23KB
  186. vhdl/LatticeORCA/lang.dat 23KB
  187. vhdl/QuickL/lang.dat 23KB
  188. vhdl/Triscend/lang.dat 23KB
  189. vhdl/Xilinx/lang.dat 23KB
  190. lang.dat 23KB
  191. VERILOG/Altera/data1.hdr 22KB
  192. vhdl/ChipExpress/data1.hdr 21KB
  193. vhdl/LatticeCPLD/data1.hdr 21KB
  194. VERILOG/Actel/data1.hdr 19KB
  195. SCH/Xilinx/_user1.cab 18KB
  196. VERILOG/Actel/_user1.cab 18KB
  197. VERILOG/Altera/_user1.cab 18KB
  198. VERILOG/Atmel/_user1.cab 18KB
  199. VERILOG/ChipExpress/_user1.cab 18KB
  200. VERILOG/Cypress/_user1.cab 18KB
  201. VERILOG/LatticeCPLD/_user1.cab 18KB
  202. VERILOG/LatticeORCA/_user1.cab 18KB
  203. VERILOG/QuickL/_user1.cab 18KB
  204. VERILOG/Triscend/_user1.cab 18KB
  205. VERILOG/Xilinx/_user1.cab 18KB
  206. vhdl/Actel/_user1.cab 18KB
  207. vhdl/Altera/_user1.cab 18KB
  208. vhdl/Atmel/_user1.cab 18KB
  209. vhdl/ChipExpress/_user1.cab 18KB
  210. vhdl/Cypress/_user1.cab 18KB
  211. vhdl/LatticeCPLD/_user1.cab 18KB
  212. vhdl/LatticeORCA/_user1.cab 18KB
  213. vhdl/QuickL/_user1.cab 18KB
  214. vhdl/Triscend/_user1.cab 18KB
  215. vhdl/Xilinx/_user1.cab 18KB
  216. vhdl/Actel/data1.hdr 17KB
  217. rel00035.gif 15KB
  218. vhdl/LatticeORCA/data1.hdr 12KB
  219. aldec_bg.gif 10KB
  220. VERILOG/ChipExpress/data1.hdr 10KB
  221. Image1.gif 10KB
  222. vhdl/Atmel/data1.hdr 9KB
  223. image6.gif 9KB
  224. crack/license.dat 9KB
  225. image7.gif 9KB
  226. image8.gif 9KB
  227. image3.gif 8KB
  228. Relnotes.css 8KB
  229. image4.gif 8KB
  230. Rel00008.gif 7KB
  231. Image2.gif 7KB
  232. VERILOG/QuickL/data1.hdr 7KB
  233. vhdl/QuickL/data1.hdr 6KB
  234. vhdl/Cypress/data1.hdr 6KB
  235. image5.gif 6KB
  236. VERILOG/Cypress/data1.hdr 5KB
  237. Rel00007.gif 5KB
  238. legends.nfo 5KB
  239. VERILOG/Triscend/data1.hdr 4KB
  240. vhdl/Triscend/data1.hdr 4KB
  241. SCH/Xilinx/_user1.hdr 4KB
  242. VERILOG/Actel/_user1.hdr 4KB
  243. VERILOG/Altera/_user1.hdr 4KB
  244. VERILOG/Atmel/_user1.hdr 4KB
  245. VERILOG/ChipExpress/_user1.hdr 4KB
  246. VERILOG/Cypress/_user1.hdr 4KB
  247. VERILOG/LatticeCPLD/_user1.hdr 4KB
  248. VERILOG/LatticeORCA/_user1.hdr 4KB
  249. VERILOG/QuickL/_user1.hdr 4KB
  250. VERILOG/Triscend/_user1.hdr 4KB
  251. VERILOG/Xilinx/_user1.hdr 4KB
  252. vhdl/Actel/_user1.hdr 4KB
  253. vhdl/Altera/_user1.hdr 4KB
  254. vhdl/Atmel/_user1.hdr 4KB
  255. vhdl/ChipExpress/_user1.hdr 4KB
  256. vhdl/Cypress/_user1.hdr 4KB
  257. vhdl/LatticeCPLD/_user1.hdr 4KB
  258. vhdl/LatticeORCA/_user1.hdr 4KB
  259. vhdl/QuickL/_user1.hdr 4KB
  260. vhdl/Triscend/_user1.hdr 4KB
  261. vhdl/Xilinx/_user1.hdr 4KB
  262. SCH/Xilinx/_sys1.hdr 4KB
  263. VERILOG/Actel/_sys1.hdr 4KB
  264. VERILOG/Altera/_sys1.hdr 4KB
  265. VERILOG/Atmel/_sys1.hdr 4KB
  266. VERILOG/ChipExpress/_sys1.hdr 4KB
  267. VERILOG/Cypress/_sys1.hdr 4KB
  268. VERILOG/LatticeCPLD/_sys1.hdr 4KB
  269. VERILOG/LatticeORCA/_sys1.hdr 4KB
  270. VERILOG/QuickL/_sys1.hdr 4KB
  271. VERILOG/Triscend/_sys1.hdr 4KB
  272. VERILOG/Xilinx/_sys1.hdr 4KB
  273. vhdl/Actel/_sys1.hdr 4KB
  274. vhdl/Altera/_sys1.hdr 4KB
  275. vhdl/Atmel/_sys1.hdr 4KB
  276. vhdl/ChipExpress/_sys1.hdr 4KB
  277. vhdl/Cypress/_sys1.hdr 4KB
  278. vhdl/LatticeCPLD/_sys1.hdr 4KB
  279. vhdl/LatticeORCA/_sys1.hdr 4KB
  280. vhdl/QuickL/_sys1.hdr 4KB
  281. vhdl/Triscend/_sys1.hdr 4KB
  282. vhdl/Xilinx/_sys1.hdr 4KB
  283. licupdnfo.html 2KB
  284. ReadMe_rus.txt 1KB
  285. layout.bin 1KB
  286. crack/readme.nfo 703B
  287. license.html 638B
  288. SCH/Xilinx/layout.bin 609B
  289. VERILOG/Actel/layout.bin 609B
  290. VERILOG/Altera/layout.bin 609B
  291. VERILOG/Atmel/layout.bin 609B
  292. VERILOG/ChipExpress/layout.bin 609B
  293. VERILOG/Cypress/layout.bin 609B
  294. VERILOG/LatticeCPLD/layout.bin 609B
  295. VERILOG/LatticeORCA/layout.bin 609B
  296. VERILOG/QuickL/layout.bin 609B
  297. VERILOG/Triscend/layout.bin 609B
  298. VERILOG/Xilinx/layout.bin 609B
  299. vhdl/Actel/layout.bin 609B
  300. vhdl/Altera/layout.bin 609B
  301. vhdl/Atmel/layout.bin 609B
  302. vhdl/ChipExpress/layout.bin 609B
  303. vhdl/Cypress/layout.bin 609B
  304. vhdl/LatticeCPLD/layout.bin 609B
  305. vhdl/LatticeORCA/layout.bin 609B
  306. vhdl/QuickL/layout.bin 609B
  307. vhdl/Triscend/layout.bin 609B
  308. vhdl/Xilinx/layout.bin 609B
  309. SCH/Xilinx/os.dat 450B
  310. VERILOG/Actel/os.dat 450B
  311. VERILOG/Altera/os.dat 450B
  312. VERILOG/Atmel/os.dat 450B
  313. VERILOG/ChipExpress/os.dat 450B
  314. VERILOG/Cypress/os.dat 450B
  315. VERILOG/LatticeCPLD/os.dat 450B
  316. VERILOG/LatticeORCA/os.dat 450B
  317. VERILOG/QuickL/os.dat 450B
  318. VERILOG/Triscend/os.dat 450B
  319. VERILOG/Xilinx/os.dat 450B
  320. vhdl/Actel/os.dat 450B
  321. vhdl/Altera/os.dat 450B
  322. vhdl/Atmel/os.dat 450B
  323. vhdl/ChipExpress/os.dat 450B
  324. vhdl/Cypress/os.dat 450B
  325. vhdl/LatticeCPLD/os.dat 450B
  326. vhdl/LatticeORCA/os.dat 450B
  327. vhdl/QuickL/os.dat 450B
  328. vhdl/Triscend/os.dat 450B
  329. vhdl/Xilinx/os.dat 450B
  330. os.dat 450B
  331. file_id.diz 432B
  332. ReleaseN.htm 404B
  333. VERILOG/ChipExpress/SETUP.INI 111B
  334. VERILOG/LatticeCPLD/SETUP.INI 111B
  335. VERILOG/LatticeORCA/SETUP.INI 111B
  336. VERILOG/QuickL/SETUP.INI 109B
  337. vhdl/ChipExpress/SETUP.INI 108B
  338. vhdl/LatticeCPLD/SETUP.INI 108B
  339. vhdl/LatticeORCA/SETUP.INI 108B
  340. SCH/Xilinx/SETUP.INI 107B
  341. VERILOG/Triscend/SETUP.INI 107B
  342. VERILOG/Cypress/SETUP.INI 106B
  343. vhdl/QuickL/SETUP.INI 106B
  344. VERILOG/Altera/SETUP.INI 105B
  345. VERILOG/Xilinx/SETUP.INI 105B
  346. VERILOG/Actel/SETUP.INI 104B
  347. VERILOG/Atmel/SETUP.INI 104B
  348. vhdl/Triscend/SETUP.INI 104B
  349. vhdl/Cypress/SETUP.INI 103B
  350. vhdl/Altera/SETUP.INI 102B
  351. vhdl/Xilinx/SETUP.INI 102B
  352. vhdl/Actel/SETUP.INI 101B
  353. vhdl/Atmel/SETUP.INI 101B
  354. SETUP.INI 100B
  355. DATA.TAG 97B
  356. A35reg.htm 90B
  357. SCH/Xilinx/DATA.TAG 87B
  358. VERILOG/Actel/DATA.TAG 87B
  359. VERILOG/Altera/DATA.TAG 87B
  360. VERILOG/Atmel/DATA.TAG 87B
  361. VERILOG/ChipExpress/DATA.TAG 87B
  362. VERILOG/Cypress/DATA.TAG 87B
  363. VERILOG/LatticeCPLD/DATA.TAG 87B
  364. VERILOG/LatticeORCA/DATA.TAG 87B
  365. VERILOG/QuickL/DATA.TAG 87B
  366. VERILOG/Triscend/DATA.TAG 87B
  367. VERILOG/Xilinx/DATA.TAG 87B
  368. vhdl/Actel/DATA.TAG 87B
  369. vhdl/Altera/DATA.TAG 87B
  370. vhdl/Atmel/DATA.TAG 87B
  371. vhdl/ChipExpress/DATA.TAG 87B
  372. vhdl/Cypress/DATA.TAG 87B
  373. vhdl/LatticeCPLD/DATA.TAG 87B
  374. vhdl/LatticeORCA/DATA.TAG 87B
  375. vhdl/QuickL/DATA.TAG 87B
  376. vhdl/Triscend/DATA.TAG 87B
  377. vhdl/Xilinx/DATA.TAG 87B
  378. SCH/Xilinx/setup.lid 49B
  379. VERILOG/Actel/setup.lid 49B
  380. VERILOG/Altera/setup.lid 49B
  381. VERILOG/Atmel/setup.lid 49B
  382. VERILOG/ChipExpress/setup.lid 49B
  383. VERILOG/Cypress/setup.lid 49B
  384. VERILOG/LatticeCPLD/setup.lid 49B
  385. VERILOG/LatticeORCA/setup.lid 49B
  386. VERILOG/QuickL/setup.lid 49B
  387. VERILOG/Triscend/setup.lid 49B
  388. VERILOG/Xilinx/setup.lid 49B
  389. vhdl/Actel/setup.lid 49B
  390. vhdl/Altera/setup.lid 49B
  391. vhdl/Atmel/setup.lid 49B
  392. vhdl/ChipExpress/setup.lid 49B
  393. vhdl/Cypress/setup.lid 49B
  394. vhdl/LatticeCPLD/setup.lid 49B
  395. vhdl/LatticeORCA/setup.lid 49B
  396. vhdl/QuickL/setup.lid 49B
  397. vhdl/Triscend/setup.lid 49B
  398. vhdl/Xilinx/setup.lid 49B
  399. setup.lid 49B
  400. vssver.scc 48B
  401. SCH/Xilinx/build.nfo 17B
  402. VERILOG/Actel/build.nfo 17B
  403. VERILOG/Altera/build.nfo 17B
  404. VERILOG/Atmel/build.nfo 17B
  405. VERILOG/ChipExpress/build.nfo 17B
  406. VERILOG/Cypress/build.nfo 17B
  407. VERILOG/LatticeCPLD/build.nfo 17B
  408. VERILOG/LatticeORCA/build.nfo 17B
  409. VERILOG/QuickL/build.nfo 17B
  410. VERILOG/Triscend/build.nfo 17B
  411. VERILOG/Xilinx/build.nfo 17B
  412. vhdl/Actel/build.nfo 17B
  413. vhdl/Altera/build.nfo 17B
  414. vhdl/Atmel/build.nfo 17B
  415. vhdl/ChipExpress/build.nfo 17B
  416. vhdl/Cypress/build.nfo 17B
  417. vhdl/LatticeCPLD/build.nfo 17B
  418. vhdl/LatticeORCA/build.nfo 17B
  419. vhdl/QuickL/build.nfo 17B
  420. vhdl/Triscend/build.nfo 17B
  421. vhdl/Xilinx/build.nfo 17B
  422. build.nfo 17B