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[ ] Udemy - Digital Timing Basics For Vlsi Interview and Soc Design

  • 收录时间:2023-06-21 14:47:04
  • 文件大小:826MB
  • 下载次数:1
  • 最近下载:2023-06-21 14:47:04
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文件列表

  1. ~Get Your Files Here !/7 - Frequency vs Voltage in SoC/30 - FV Curve Explanation.mp4 66MB
  2. ~Get Your Files Here !/4 - Problem Solving for Interview/15 - Setup Violation Fix Clock Path Delay.mp4 54MB
  3. ~Get Your Files Here !/3 - Static Timing Foundation/12 - Example for Setup & Hold Condition.mp4 48MB
  4. ~Get Your Files Here !/9 - Practical Design Issue 2 Max & Min Frequency of Operation/38 - Maximum Frequency of Operation with Clock Skew.mp4 38MB
  5. ~Get Your Files Here !/5 - Advanced Concepts for Interview Timing Margins/23 - Clock Gating Setup & Hold Time.mp4 38MB
  6. ~Get Your Files Here !/5 - Advanced Concepts for Interview Timing Margins/21 - Positive Latch Setup & Hold Time.mp4 37MB
  7. ~Get Your Files Here !/5 - Advanced Concepts for Interview Timing Margins/24 - Negative Hold Time for Flop.mp4 35MB
  8. ~Get Your Files Here !/4 - Problem Solving for Interview/19 - Latency Reduction with Optimized Design.mp4 35MB
  9. ~Get Your Files Here !/3 - Static Timing Foundation/11 - Hold Time Condition in Cycle Path.mp4 31MB
  10. ~Get Your Files Here !/4 - Problem Solving for Interview/18 - Good Margin but Higher Latency.mp4 30MB
  11. ~Get Your Files Here !/1 - Introduction/1 - Introduction.mp4 30MB
  12. ~Get Your Files Here !/5 - Advanced Concepts for Interview Timing Margins/25 - Negative Setup Time for Flop.mp4 26MB
  13. ~Get Your Files Here !/4 - Problem Solving for Interview/14 - Setup Violation.mp4 24MB
  14. ~Get Your Files Here !/3 - Static Timing Foundation/10 - Setup Time Condition in Cycle Path.mp4 24MB
  15. ~Get Your Files Here !/5 - Advanced Concepts for Interview Timing Margins/22 - Negative Latch Setup & Hold Time.mp4 24MB
  16. ~Get Your Files Here !/4 - Problem Solving for Interview/17 - Hold Violation Fix Data Path Delay.mp4 19MB
  17. ~Get Your Files Here !/4 - Problem Solving for Interview/13 - Setup & Hold Margin Computation.mp4 19MB
  18. ~Get Your Files Here !/4 - Problem Solving for Interview/20 - Design Issues in Real World SoC.mp4 18MB
  19. ~Get Your Files Here !/8 - Practical Design Issue1 Multiple Parallel Paths/33 - Multiple Path Hold Time Analysis.mp4 18MB
  20. ~Get Your Files Here !/8 - Practical Design Issue1 Multiple Parallel Paths/32 - Multiple Path Setup Time Analysis.mp4 17MB
  21. ~Get Your Files Here !/9 - Practical Design Issue 2 Max & Min Frequency of Operation/36 - Minimum Frequency of Operation.mp4 16MB
  22. ~Get Your Files Here !/3 - Static Timing Foundation/9 - Physical Implementation.mp4 16MB
  23. ~Get Your Files Here !/7 - Frequency vs Voltage in SoC/29 - FV Curve Introduction.mp4 16MB
  24. ~Get Your Files Here !/4 - Problem Solving for Interview/16 - Hold Violation.mp4 15MB
  25. ~Get Your Files Here !/6 - Common Misconceptions/26 - Setup Hold Clk2Q and Clock Skew.mp4 14MB
  26. ~Get Your Files Here !/8 - Practical Design Issue1 Multiple Parallel Paths/34 - Multiple Path Summary.mp4 14MB
  27. ~Get Your Files Here !/2 - Understanding Flop Timings/3 - Quick Summary.mp4 14MB
  28. ~Get Your Files Here !/6 - Common Misconceptions/28 - Setup Margin with Frequency.mp4 12MB
  29. ~Get Your Files Here !/2 - Understanding Flop Timings/4 - Setup Time & Setup Margin.mp4 12MB
  30. ~Get Your Files Here !/3 - Static Timing Foundation/7 - Buffer.mp4 11MB
  31. ~Get Your Files Here !/9 - Practical Design Issue 2 Max & Min Frequency of Operation/35 - Frequency of Operation.mp4 10MB
  32. ~Get Your Files Here !/9 - Practical Design Issue 2 Max & Min Frequency of Operation/37 - Maximum Frequency of Operation without Clock Skew.mp4 9MB
  33. ~Get Your Files Here !/2 - Understanding Flop Timings/5 - Hold time & Hold Margin.mp4 9MB
  34. ~Get Your Files Here !/6 - Common Misconceptions/27 - Hold Margin with Frequency.mp4 9MB
  35. ~Get Your Files Here !/8 - Practical Design Issue1 Multiple Parallel Paths/31 - Multiple Path Problem Statement.mp4 6MB
  36. ~Get Your Files Here !/2 - Understanding Flop Timings/2 - Basic Definitions.mp4 4MB
  37. ~Get Your Files Here !/10 - Quiz & Next Step/39 - Next Step.mp4 4MB
  38. ~Get Your Files Here !/2 - Understanding Flop Timings/6 - Clock to Q Delay.mp4 4MB
  39. ~Get Your Files Here !/3 - Static Timing Foundation/8 - Logic Implementation.mp4 2MB
  40. ~Get Your Files Here !/7 - Frequency vs Voltage in SoC/30 - FV Curve Explanation English.srt 26KB
  41. ~Get Your Files Here !/3 - Static Timing Foundation/12 - Example for Setup & Hold Condition English.srt 17KB
  42. ~Get Your Files Here !/5 - Advanced Concepts for Interview Timing Margins/21 - Positive Latch Setup & Hold Time English.srt 14KB
  43. ~Get Your Files Here !/5 - Advanced Concepts for Interview Timing Margins/24 - Negative Hold Time for Flop English.srt 14KB
  44. ~Get Your Files Here !/9 - Practical Design Issue 2 Max & Min Frequency of Operation/38 - Maximum Frequency of Operation with Clock Skew English.srt 13KB
  45. ~Get Your Files Here !/4 - Problem Solving for Interview/15 - Setup Violation Fix Clock Path Delay English.srt 13KB
  46. ~Get Your Files Here !/4 - Problem Solving for Interview/20 - Design Issues in Real World SoC English.srt 10KB
  47. ~Get Your Files Here !/3 - Static Timing Foundation/11 - Hold Time Condition in Cycle Path English.srt 10KB
  48. ~Get Your Files Here !/5 - Advanced Concepts for Interview Timing Margins/25 - Negative Setup Time for Flop English.srt 10KB
  49. ~Get Your Files Here !/3 - Static Timing Foundation/10 - Setup Time Condition in Cycle Path English.srt 9KB
  50. ~Get Your Files Here !/4 - Problem Solving for Interview/18 - Good Margin but Higher Latency English.srt 9KB
  51. ~Get Your Files Here !/4 - Problem Solving for Interview/19 - Latency Reduction with Optimized Design English.srt 8KB
  52. ~Get Your Files Here !/7 - Frequency vs Voltage in SoC/29 - FV Curve Introduction English.srt 8KB
  53. ~Get Your Files Here !/3 - Static Timing Foundation/9 - Physical Implementation English.srt 8KB
  54. ~Get Your Files Here !/4 - Problem Solving for Interview/13 - Setup & Hold Margin Computation English.srt 7KB
  55. ~Get Your Files Here !/4 - Problem Solving for Interview/17 - Hold Violation Fix Data Path Delay English.srt 7KB
  56. ~Get Your Files Here !/8 - Practical Design Issue1 Multiple Parallel Paths/33 - Multiple Path Hold Time Analysis English.srt 7KB
  57. ~Get Your Files Here !/4 - Problem Solving for Interview/16 - Hold Violation English.srt 6KB
  58. ~Get Your Files Here !/2 - Understanding Flop Timings/3 - Quick Summary English.srt 6KB
  59. ~Get Your Files Here !/6 - Common Misconceptions/26 - Setup Hold Clk2Q and Clock Skew English.srt 6KB
  60. ~Get Your Files Here !/8 - Practical Design Issue1 Multiple Parallel Paths/32 - Multiple Path Setup Time Analysis English.srt 6KB
  61. ~Get Your Files Here !/6 - Common Misconceptions/28 - Setup Margin with Frequency English.srt 6KB
  62. ~Get Your Files Here !/9 - Practical Design Issue 2 Max & Min Frequency of Operation/36 - Minimum Frequency of Operation English.srt 5KB
  63. ~Get Your Files Here !/2 - Understanding Flop Timings/4 - Setup Time & Setup Margin English.srt 5KB
  64. ~Get Your Files Here !/8 - Practical Design Issue1 Multiple Parallel Paths/34 - Multiple Path Summary English.srt 5KB
  65. ~Get Your Files Here !/3 - Static Timing Foundation/7 - Buffer English.srt 5KB
  66. ~Get Your Files Here !/6 - Common Misconceptions/27 - Hold Margin with Frequency English.srt 5KB
  67. ~Get Your Files Here !/2 - Understanding Flop Timings/5 - Hold time & Hold Margin English.srt 4KB
  68. ~Get Your Files Here !/9 - Practical Design Issue 2 Max & Min Frequency of Operation/37 - Maximum Frequency of Operation without Clock Skew English.srt 3KB
  69. ~Get Your Files Here !/2 - Understanding Flop Timings/6 - Clock to Q Delay English.srt 2KB
  70. ~Get Your Files Here !/3 - Static Timing Foundation/8 - Logic Implementation English.srt 1KB
  71. ~Get Your Files Here !/10 - Quiz & Next Step/39 - Next Step English.srt 806B
  72. ~Get Your Files Here !/Bonus Resources.txt 386B
  73. Get Bonus Downloads Here.url 182B