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uc-berkeley-cs61c-great-ideas-in-computer-architecture

  • 收录时间:2022-02-03 08:43:34
  • 文件大小:714MB
  • 下载次数:1
  • 最近下载:2022-02-03 08:43:34
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文件列表

  1. 30-pipelining-2.mp3 12MB
  2. 37-networks.mp3 12MB
  3. 22-combinational-logic-2.mp3 12MB
  4. 33-caches-3.mp3 12MB
  5. 27-cpu-control-design-1.mp3 12MB
  6. 03-introduction-to-c.mp3 12MB
  7. 20-introduction-to-synchronous-digital-systems.mp3 12MB
  8. 39-performance-1.mp3 12MB
  9. 34-virtual-memory-1.mp3 12MB
  10. 41-introduction-to-reconfigurable-computing.mp3 12MB
  11. 28-cpu-control-design-2.mp3 12MB
  12. 10-mips-branch-instructions-2.mp3 12MB
  13. 16-floating-point-2.mp3 11MB
  14. 07-memory-management-2.mp3 11MB
  15. 36-io.mp3 11MB
  16. 23-combinational-logic-blocks-1.mp3 11MB
  17. 38-disks.mp3 11MB
  18. 19-compilation-assembly-linking-2.mp3 11MB
  19. 15-floating-point-1.mp3 11MB
  20. 32-caches-2.mp3 11MB
  21. 06-memory-management-1.mp3 11MB
  22. 39-performance-2.mp3 11MB
  23. 35-virtual-memory-2.mp3 11MB
  24. 13-mips-instruction-representation-1.mp3 11MB
  25. 21-state-elements.mp3 11MB
  26. 02-number-representation.mp3 11MB
  27. 31-caches-1.mp3 11MB
  28. 12-mips-procedures-2-and-logical-ops.mp3 11MB
  29. 14-mips-instruction-representation-2.mp3 11MB
  30. 26-cpu-datapath-design-2.mp3 11MB
  31. 25-cpu-datapath-design-1.mp3 11MB
  32. 01-course-introduction.mp3 11MB
  33. 05-c-structs-and-memory-management.mp3 11MB
  34. 08-introduction-to-mips.mp3 11MB
  35. 29-pipelining-1.mp3 11MB
  36. 09-mips-load-store-and-branch-instructions-1.mp3 11MB
  37. 18-compilation-assembly-linking-1.mp3 10MB
  38. 04-c-pointers-and-arrays.mp3 10MB
  39. 11-mips-procedures-1.mp3 10MB
  40. 42-class-summary.mp3 10MB
  41. 03-notes-on-c-harvey_jp2.zip 10MB
  42. 17-mips-instruction-representation-3.mp3 10MB
  43. 24-combinational-logic-blocks-2.mp3 10MB
  44. 22-combinational-logic-1.mp3 9MB
  45. 07-hilfinger-notes_jp2.zip 9MB
  46. 40-x86.mp3 8MB
  47. 38-disks.pdf 6MB
  48. 31-caches-1_jp2.zip 5MB
  49. 40-x86_jp2.zip 4MB
  50. 19-compilation-assembly-linking-2_jp2.zip 4MB
  51. 41-introduction-to-reconfigurable-computing.ppt 4MB
  52. 36-io_jp2.zip 4MB
  53. mars/mars.jar 4MB
  54. 38-disks_jp2.zip 4MB
  55. 39-performance_jp2.zip 4MB
  56. 22-combinational-logic_jp2.zip 4MB
  57. 12-mips-procedures-2-and-logical-ops_jp2.zip 4MB
  58. 06-c-memory-management-1_jp2.zip 4MB
  59. 07-c-memory-management-2_jp2.zip 4MB
  60. 30-pipelining-2_jp2.zip 3MB
  61. 35-virtual-memory-2_jp2.zip 3MB
  62. 28-cpu-control-design-2_jp2.zip 3MB
  63. 29-pipelining-1_jp2.zip 3MB
  64. 33-caches-3_jp2.zip 3MB
  65. 17-mips-instruction-representation-3_jp2.zip 3MB
  66. 23-combinational-logic-blocks-1_jp2.zip 3MB
  67. 24-combinational-logic-blocks-2_jp2.zip 3MB
  68. 15-floating-point-1_jp2.zip 3MB
  69. 34-virtual-memory-1_jp2.zip 3MB
  70. 01-course-introduction_jp2.zip 3MB
  71. 37-networks_jp2.zip 3MB
  72. 02-number-representation_jp2.zip 3MB
  73. 16-floating-point-2_jp2.zip 3MB
  74. 13-mips-instruction-representation-1_jp2.zip 3MB
  75. 32-caches-2_jp2.zip 3MB
  76. 22-boolean-logic_jp2.zip 3MB
  77. 08-introduction-to-mips_jp2.zip 3MB
  78. 18-compilation-assembly-linking-1_jp2.zip 3MB
  79. 09-mips-load-store-and-branch-instructions-1_jp2.zip 3MB
  80. 10-mips-branch-instructions-2_jp2.zip 3MB
  81. 25-cpu-datapath-design-1_jp2.zip 3MB
  82. 20-introduction-to-synchronous-digital-systems.pdf 3MB
  83. 04-c-pointers-and-arrays_jp2.zip 2MB
  84. 14-mips-instruction-representation-2_jp2.zip 2MB
  85. 26-cpu-datapath-design-2_jp2.zip 2MB
  86. 11-mips-procedures-1_jp2.zip 2MB
  87. 05-c-structs-and-memory-management_jp2.zip 2MB
  88. 03-introduction-to-c_jp2.zip 2MB
  89. 21-state-elements_jp2.zip 2MB
  90. 27-cpu-control-design-1_jp2.zip 2MB
  91. 33-caches-3.pdf 2MB
  92. 21-state-elements.pdf 2MB
  93. 23-blocks_jp2.zip 2MB
  94. 24-blocks_jp2.zip 2MB
  95. 20-introduction-to-synchronous-digital-systems_jp2.zip 1MB
  96. 22-combinational-logic.pdf 1MB
  97. 03-notes-on-c-harvey_hocr.html 1MB
  98. 07-hilfinger-notes_hocr.html 1MB
  99. 23-blocks.pdf 1MB
  100. 24-blocks.pdf 1MB
  101. 37-networks.pdf 758KB
  102. 03-notes-on-c-harvey_djvu.xml 681KB
  103. 03-notes-on-c-harvey_chocr.html.gz 657KB
  104. 07-hilfinger-notes_djvu.xml 622KB
  105. 07-hilfinger-notes_chocr.html.gz 614KB
  106. 40-x86_hocr.html 559KB
  107. 01-course-introduction.pdf 521KB
  108. 37-networks_hocr.html 498KB
  109. 31-caches-1_hocr.html 494KB
  110. 36-io_hocr.html 485KB
  111. 19-compilation-assembly-linking-2_hocr.html 468KB
  112. 23-combinational-logic-blocks-1.pdf 461KB
  113. 24-combinational-logic-blocks-2.pdf 461KB
  114. 38-disks_hocr.html 443KB
  115. 12-mips-procedures-2-and-logical-ops_hocr.html 430KB
  116. 01-course-introduction_hocr.html 420KB
  117. 35-virtual-memory-2_hocr.html 409KB
  118. 06-c-memory-management-1_hocr.html 405KB
  119. 07-c-memory-management-2_hocr.html 405KB
  120. 32-caches-2_hocr.html 402KB
  121. 28-cpu-control-design-2_hocr.html 399KB
  122. 23-combinational-logic-blocks-1_hocr.html 393KB
  123. 24-combinational-logic-blocks-2_hocr.html 393KB
  124. 39-performance_hocr.html 389KB
  125. 02-number-representation_hocr.html 387KB
  126. 22-boolean-logic_hocr.html 385KB
  127. 33-caches-3_hocr.html 366KB
  128. 08-introduction-to-mips.pdf 362KB
  129. 22-boolean-logic.pdf 353KB
  130. 29-pipelining-1_hocr.html 352KB
  131. 05-c-structs-and-memory-management_hocr.html 348KB
  132. 08-introduction-to-mips_hocr.html 347KB
  133. 17-mips-instruction-representation-3_hocr.html 345KB
  134. 30-pipelining-2_hocr.html 343KB
  135. 03-introduction-to-c.pdf 338KB
  136. 16-floating-point-2_hocr.html 335KB
  137. 15-floating-point-1_hocr.html 331KB
  138. 13-mips-instruction-representation-1_hocr.html 327KB
  139. 39-performance.pdf 309KB
  140. 14-mips-instruction-representation-2_hocr.html 306KB
  141. 18-compilation-assembly-linking-1_hocr.html 305KB
  142. 34-virtual-memory-1_hocr.html 305KB
  143. 09-mips-load-store-and-branch-instructions-1_hocr.html 304KB
  144. 30-pipelining-2.pdf 302KB
  145. 10-mips-branch-instructions-2_hocr.html 297KB
  146. 25-cpu-datapath-design-1_hocr.html 296KB
  147. 36-io.pdf 293KB
  148. 22-combinational-logic_hocr.html 292KB
  149. 26-cpu-datapath-design-2_hocr.html 291KB
  150. 04-c-pointers-and-arrays_hocr.html 291KB
  151. 04-c-pointers-and-arrays_spectrogram.png 285KB
  152. 24-combinational-logic-blocks-2_spectrogram.png 284KB
  153. 05-c-structs-and-memory-management_spectrogram.png 279KB
  154. 18-compilation-assembly-linking-1_spectrogram.png 278KB
  155. 17-mips-instruction-representation-3_spectrogram.png 278KB
  156. 36-io_spectrogram.png 277KB
  157. 12-mips-procedures-2-and-logical-ops_spectrogram.png 276KB
  158. 42-class-summary_spectrogram.png 276KB
  159. 10-mips-branch-instructions-2_spectrogram.png 276KB
  160. 26-cpu-datapath-design-2_spectrogram.png 276KB
  161. 06-memory-management-1_spectrogram.png 276KB
  162. 03-introduction-to-c_spectrogram.png 275KB
  163. 39-performance-1_spectrogram.png 275KB
  164. 35-virtual-memory-2_spectrogram.png 275KB
  165. 21-state-elements_spectrogram.png 275KB
  166. 27-cpu-control-design-1_spectrogram.png 274KB
  167. 16-floating-point-2_spectrogram.png 274KB
  168. 09-mips-load-store-and-branch-instructions-1_spectrogram.png 274KB
  169. 33-caches-3_spectrogram.png 274KB
  170. 23-combinational-logic-blocks-1_spectrogram.png 274KB
  171. 29-pipelining-1_spectrogram.png 274KB
  172. 22-combinational-logic-1_spectrogram.png 274KB
  173. 40-x86_spectrogram.png 273KB
  174. 03-introduction-to-c_hocr.html 273KB
  175. 34-virtual-memory-1_spectrogram.png 273KB
  176. 20-introduction-to-synchronous-digital-systems_spectrogram.png 273KB
  177. 11-mips-procedures-1_spectrogram.png 272KB
  178. 29-pipelining-1.pdf 272KB
  179. 39-performance-2_spectrogram.png 272KB
  180. 19-compilation-assembly-linking-2_spectrogram.png 272KB
  181. uc-berkeley-cs61c-great-ideas-in-computer-architecture_meta.sqlite 272KB
  182. 37-networks_spectrogram.png 272KB
  183. 28-cpu-control-design-2_spectrogram.png 271KB
  184. 22-combinational-logic-2_spectrogram.png 271KB
  185. 13-mips-instruction-representation-1_spectrogram.png 271KB
  186. 25-cpu-datapath-design-1_spectrogram.png 271KB
  187. 07-memory-management-2_spectrogram.png 270KB
  188. 38-disks_spectrogram.png 269KB
  189. 31-caches-1_spectrogram.png 267KB
  190. 30-pipelining-2_spectrogram.png 267KB
  191. 08-introduction-to-mips_spectrogram.png 267KB
  192. 15-floating-point-1_spectrogram.png 266KB
  193. 32-caches-2_spectrogram.png 265KB
  194. 02-number-representation_spectrogram.png 265KB
  195. 41-introduction-to-reconfigurable-computing_spectrogram.png 263KB
  196. 28-cpu-control-design-2.pdf 260KB
  197. 40-x86_djvu.xml 259KB
  198. 11-mips-procedures-1_hocr.html 259KB
  199. 01-course-introduction_spectrogram.png 259KB
  200. 27-cpu-control-design-1_hocr.html 256KB
  201. 21-state-elements_hocr.html 254KB
  202. 40-x86_chocr.html.gz 244KB
  203. 31-caches-1.pdf 243KB
  204. 40-x86.pdf 242KB
  205. 37-networks_djvu.xml 236KB
  206. 35-virtual-memory-2.pdf 225KB
  207. 31-caches-1_djvu.xml 223KB
  208. 07-hilfinger-notes.pdf 223KB
  209. 37-networks_chocr.html.gz 222KB
  210. 36-io_djvu.xml 220KB
  211. 19-compilation-assembly-linking-2_djvu.xml 216KB
  212. 12-mips-procedures-2-and-logical-ops_djvu.xml 211KB
  213. 23-combinational-logic-blocks-1_djvu.xml 210KB
  214. 24-combinational-logic-blocks-2_djvu.xml 210KB
  215. 38-disks_djvu.xml 204KB
  216. 36-io_chocr.html.gz 203KB
  217. 19-compilation-assembly-linking-2_chocr.html.gz 199KB
  218. 22-boolean-logic_djvu.xml 196KB
  219. 31-caches-1_chocr.html.gz 196KB
  220. 32-caches-2.pdf 193KB
  221. 23-blocks_hocr.html 192KB
  222. 24-blocks_hocr.html 192KB
  223. 26-cpu-datapath-design-2.pdf 189KB
  224. 06-c-memory-management-1_djvu.xml 189KB
  225. 07-c-memory-management-2_djvu.xml 189KB
  226. 12-mips-procedures-2-and-logical-ops_chocr.html.gz 188KB
  227. 39-performance_djvu.xml 187KB
  228. 10-mips-branch-instructions-2.pdf 185KB
  229. 19-compilation-assembly-linking-2.pdf 184KB
  230. 23-combinational-logic-blocks-1_chocr.html.gz 184KB
  231. 24-combinational-logic-blocks-2_chocr.html.gz 184KB
  232. 39-performance_chocr.html.gz 182KB
  233. 38-disks_chocr.html.gz 181KB
  234. 22-boolean-logic_chocr.html.gz 181KB
  235. 32-caches-2_djvu.xml 179KB
  236. 35-virtual-memory-2_djvu.xml 178KB
  237. 27-cpu-control-design-1.pdf 178KB
  238. 34-virtual-memory-1.pdf 177KB
  239. 01-course-introduction_djvu.xml 176KB
  240. 16-floating-point-2.pdf 175KB
  241. 06-c-memory-management-1.pdf 172KB
  242. 07-c-memory-management-2.pdf 172KB
  243. 12-mips-procedures-2-and-logical-ops.pdf 171KB
  244. 02-number-representation_djvu.xml 171KB
  245. 09-mips-load-store-and-branch-instructions-1.pdf 170KB
  246. 06-c-memory-management-1_chocr.html.gz 170KB
  247. 07-c-memory-management-2_chocr.html.gz 170KB
  248. 28-cpu-control-design-2_djvu.xml 169KB
  249. 33-caches-3_djvu.xml 167KB
  250. 25-cpu-datapath-design-1.pdf 164KB
  251. 08-introduction-to-mips_djvu.xml 162KB
  252. 29-pipelining-1_djvu.xml 161KB
  253. 13-mips-instruction-representation-1_djvu.xml 159KB
  254. 15-floating-point-1_djvu.xml 159KB
  255. 20-introduction-to-synchronous-digital-systems_hocr.html 158KB
  256. 16-floating-point-2_djvu.xml 157KB
  257. 17-mips-instruction-representation-3_djvu.xml 156KB
  258. 05-c-structs-and-memory-management_djvu.xml 155KB
  259. 30-pipelining-2_djvu.xml 155KB
  260. 01-course-introduction_chocr.html.gz 153KB
  261. 35-virtual-memory-2_chocr.html.gz 153KB
  262. 03-notes-on-c-harvey.pdf 153KB
  263. 13-mips-instruction-representation-1_chocr.html.gz 152KB
  264. 11-mips-procedures-1.pdf 152KB
  265. 32-caches-2_chocr.html.gz 151KB
  266. 08-introduction-to-mips_chocr.html.gz 151KB
  267. 13-mips-instruction-representation-1.pdf 151KB
  268. 17-mips-instruction-representation-3_chocr.html.gz 151KB
  269. 15-floating-point-1_chocr.html.gz 150KB
  270. 18-compilation-assembly-linking-1.pdf 149KB
  271. 09-mips-load-store-and-branch-instructions-1_djvu.xml 147KB
  272. 02-number-representation_chocr.html.gz 146KB
  273. 16-floating-point-2_chocr.html.gz 146KB
  274. 18-compilation-assembly-linking-1_djvu.xml 144KB
  275. 17-mips-instruction-representation-3.pdf 144KB
  276. 05-c-structs-and-memory-management.pdf 144KB
  277. 33-caches-3_chocr.html.gz 143KB
  278. 25-cpu-datapath-design-1_djvu.xml 142KB
  279. 34-virtual-memory-1_djvu.xml 142KB
  280. 02-number-representation.pdf 141KB
  281. 10-mips-branch-instructions-2_djvu.xml 141KB
  282. 29-pipelining-1_chocr.html.gz 141KB
  283. 28-cpu-control-design-2_chocr.html.gz 140KB
  284. 04-c-pointers-and-arrays_djvu.xml 139KB
  285. 14-mips-instruction-representation-2_djvu.xml 139KB
  286. 26-cpu-datapath-design-2_djvu.xml 138KB
  287. 09-mips-load-store-and-branch-instructions-1_chocr.html.gz 137KB
  288. 18-compilation-assembly-linking-1_chocr.html.gz 137KB
  289. 04-c-pointers-and-arrays.pdf 137KB
  290. 14-mips-instruction-representation-2_spectrogram.png 137KB
  291. 30-pipelining-2_chocr.html.gz 136KB
  292. 15-floating-point-1.pdf 136KB
  293. 14-mips-instruction-representation-2.pdf 132KB
  294. 34-virtual-memory-1_chocr.html.gz 130KB
  295. 05-c-structs-and-memory-management_chocr.html.gz 130KB
  296. 03-introduction-to-c_djvu.xml 128KB
  297. 10-mips-branch-instructions-2_chocr.html.gz 127KB
  298. 25-cpu-datapath-design-1_chocr.html.gz 126KB
  299. 04-c-pointers-and-arrays_chocr.html.gz 126KB
  300. 14-mips-instruction-representation-2_chocr.html.gz 126KB
  301. 11-mips-procedures-1_djvu.xml 122KB
  302. 26-cpu-datapath-design-2_chocr.html.gz 122KB
  303. 21-state-elements_djvu.xml 118KB
  304. 27-cpu-control-design-1_djvu.xml 115KB
  305. 03-introduction-to-c_chocr.html.gz 113KB
  306. 11-mips-procedures-1_chocr.html.gz 113KB
  307. 21-state-elements_chocr.html.gz 105KB
  308. 22-combinational-logic_djvu.xml 104KB
  309. 27-cpu-control-design-1_chocr.html.gz 98KB
  310. 24-blocks_djvu.xml 87KB
  311. 23-blocks_djvu.xml 87KB
  312. 22-combinational-logic_chocr.html.gz 78KB
  313. 20-introduction-to-synchronous-digital-systems_djvu.xml 72KB
  314. 23-blocks_chocr.html.gz 71KB
  315. 24-blocks_chocr.html.gz 70KB
  316. 20-introduction-to-synchronous-digital-systems_chocr.html.gz 64KB
  317. 32-caches-2.png 63KB
  318. 15-floating-point-1.png 62KB
  319. 02-number-representation.png 61KB
  320. 31-caches-1.png 61KB
  321. 30-pipelining-2.png 60KB
  322. 01-course-introduction.png 59KB
  323. 08-introduction-to-mips.png 57KB
  324. 07-memory-management-2.png 54KB
  325. 09-mips-load-store-and-branch-instructions-1.png 54KB
  326. 03-notes-on-c-harvey_djvu.txt 52KB
  327. 10-mips-branch-instructions-2.png 48KB
  328. 22-combinational-logic-2.png 48KB
  329. 41-introduction-to-reconfigurable-computing.png 47KB
  330. 17-mips-instruction-representation-3.png 47KB
  331. 07-hilfinger-notes_djvu.txt 47KB
  332. 25-cpu-datapath-design-1.png 47KB
  333. 28-cpu-control-design-2.png 47KB
  334. 23-combinational-logic-blocks-1.png 47KB
  335. 20-introduction-to-synchronous-digital-systems.png 46KB
  336. 19-compilation-assembly-linking-2.png 46KB
  337. 39-performance-1.png 46KB
  338. 40-x86.png 46KB
  339. 39-performance-2.png 46KB
  340. 06-memory-management-1.png 46KB
  341. 16-floating-point-2.png 46KB
  342. 27-cpu-control-design-1.png 46KB
  343. 03-introduction-to-c.png 46KB
  344. 29-pipelining-1.png 46KB
  345. 18-compilation-assembly-linking-1.png 46KB
  346. 26-cpu-datapath-design-2.png 46KB
  347. 13-mips-instruction-representation-1.png 46KB
  348. 38-disks.png 45KB
  349. 34-virtual-memory-1.png 45KB
  350. 35-virtual-memory-2.png 45KB
  351. 37-networks.png 45KB
  352. 11-mips-procedures-1.png 45KB
  353. 42-class-summary.png 45KB
  354. 12-mips-procedures-2-and-logical-ops.png 45KB
  355. 05-c-structs-and-memory-management.png 45KB
  356. 04-c-pointers-and-arrays.png 45KB
  357. 36-io.png 45KB
  358. 21-state-elements.png 44KB
  359. 22-combinational-logic-1.png 44KB
  360. 24-combinational-logic-blocks-2.png 43KB
  361. 33-caches-3.png 43KB
  362. 14-mips-instruction-representation-2.png 27KB
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  364. 40-x86_djvu.txt 18KB
  365. 37-networks_djvu.txt 17KB
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  374. 39-performance_djvu.txt 13KB
  375. 38-disks_djvu.txt 13KB
  376. 06-c-memory-management-1_djvu.txt 12KB
  377. 07-c-memory-management-2_djvu.txt 12KB
  378. 13-mips-instruction-representation-1_djvu.txt 11KB
  379. 35-virtual-memory-2_djvu.txt 11KB
  380. 01-course-introduction_djvu.txt 11KB
  381. 15-floating-point-1_djvu.txt 11KB
  382. 32-caches-2_djvu.txt 11KB
  383. 08-introduction-to-mips_djvu.txt 11KB
  384. 17-mips-instruction-representation-3_djvu.txt 11KB
  385. 16-floating-point-2_djvu.txt 10KB
  386. 02-number-representation_djvu.txt 10KB
  387. 33-caches-3_djvu.txt 10KB
  388. 29-pipelining-1_djvu.txt 10KB
  389. 18-compilation-assembly-linking-1_djvu.txt 10KB
  390. 09-mips-load-store-and-branch-instructions-1_djvu.txt 10KB
  391. 30-pipelining-2_djvu.txt 10KB
  392. 28-cpu-control-design-2_djvu.txt 10KB
  393. 34-virtual-memory-1_djvu.txt 9KB
  394. 05-c-structs-and-memory-management_djvu.txt 9KB
  395. 25-cpu-datapath-design-1_djvu.txt 9KB
  396. 04-c-pointers-and-arrays_djvu.txt 9KB
  397. 10-mips-branch-instructions-2_djvu.txt 9KB
  398. 14-mips-instruction-representation-2_djvu.txt 9KB
  399. 26-cpu-datapath-design-2_djvu.txt 9KB
  400. 07-hilfinger-notes_scandata.xml 8KB
  401. 03-introduction-to-c_djvu.txt 8KB
  402. 11-mips-procedures-1_djvu.txt 8KB
  403. 21-state-elements_djvu.txt 7KB
  404. 31-caches-1_scandata.xml 7KB
  405. 27-cpu-control-design-1_djvu.txt 7KB
  406. 03-notes-on-c-harvey_scandata.xml 7KB
  407. 37-networks_hocr_searchtext.txt.gz 7KB
  408. 40-x86_hocr_searchtext.txt.gz 7KB
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  588. README.txt 62B