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[ ] Udemy - Building Custom AXI Interface Peripherals for ZYNQ Devices

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文件列表

  1. ~Get Your Files Here !/7 - Adding Interrupts with Vivado Template/37 - Using Vivado Interrupt Template Code P2.mp4 214MB
  2. ~Get Your Files Here !/8 - Adding Master Interface/45 - Creating Master Interface with Vivado Template P1.mp4 163MB
  3. ~Get Your Files Here !/7 - Adding Interrupts with Vivado Template/42 - Blinking Effect with Interrupt.mp4 151MB
  4. ~Get Your Files Here !/6 - Adding Interrupts to Slave Lite Interfaces/33 - Adding Interrupt with RTL P2.mp4 149MB
  5. ~Get Your Files Here !/10 - AXI Stream Master Interface with Vivado Template/55 - Creating AXIS Master Interface P1.mp4 145MB
  6. ~Get Your Files Here !/9 - AXI Stream Slave Interface with Vivado Template/49 - Building AXIS Slave Interface P1.mp4 139MB
  7. ~Get Your Files Here !/7 - Adding Interrupts with Vivado Template/36 - Using Vivado Interrupt Template Code P1.mp4 100MB
  8. ~Get Your Files Here !/4 - Understanding AXI4-Lite Signals/23 - Analyzing Signals on ILA Probe.mp4 98MB
  9. ~Get Your Files Here !/5 - Adding AXI Lite Interface for existing Verilog Code/25 - Add Existing RTL Delay Generator P1.mp4 94MB
  10. ~Get Your Files Here !/6 - Adding Interrupts to Slave Lite Interfaces/32 - Adding Interrupt with RTL P1.mp4 90MB
  11. ~Get Your Files Here !/4 - Understanding AXI4-Lite Signals/21 - Other Signals in Slave Lite Interface.mp4 90MB
  12. ~Get Your Files Here !/5 - Adding AXI Lite Interface for existing Verilog Code/27 - Adding Existing RTL Multiplier P1.mp4 83MB
  13. ~Get Your Files Here !/6 - Adding Interrupts to Slave Lite Interfaces/31 - Fundamentals of Interrupt C Application.mp4 81MB
  14. ~Get Your Files Here !/2 - Building AXI Slave Lite Interface Using Vivado Template without I O ports/7 - Slave Lite Interface without I O Ports P4 Creating C Application.mp4 76MB
  15. ~Get Your Files Here !/9 - AXI Stream Slave Interface with Vivado Template/50 - Building AXIS Slave Interface P2.mp4 65MB
  16. ~Get Your Files Here !/9 - AXI Stream Slave Interface with Vivado Template/52 - Building Complex FSM with existing FSM for AXIS.mp4 64MB
  17. ~Get Your Files Here !/8 - Adding Master Interface/46 - Creating Master Interface with Vivado Template P2.mp4 63MB
  18. ~Get Your Files Here !/11 - AXIS Slave Interface with Verilog/60 - Building AXIS Slave Interface with Verilog P2.mp4 62MB
  19. ~Get Your Files Here !/12 - AXIS Master Slave Interface with Verilog/64 - Building AXIS Master Slave Interface with Verilog P1.mp4 57MB
  20. ~Get Your Files Here !/7 - Adding Interrupts with Vivado Template/39 - Modifying Delay of the Vivado Interrupt Template.mp4 55MB
  21. ~Get Your Files Here !/2 - Building AXI Slave Lite Interface Using Vivado Template without I O ports/4 - Slave Lite Interface without I O Ports P1 Creating IP.mp4 55MB
  22. ~Get Your Files Here !/5 - Adding AXI Lite Interface for existing Verilog Code/29 - Adding Exisitng RTL COMPLEX FSM P1.mp4 55MB
  23. ~Get Your Files Here !/3 - Building AXI Slave Lite Interface Using Vivado Template with I O ports/11 - Adding Output port to Slave Lite Interface P1.mp4 50MB
  24. ~Get Your Files Here !/3 - Building AXI Slave Lite Interface Using Vivado Template with I O ports/15 - Adding Input and Output ports to Slave Lite Interface P2.mp4 49MB
  25. ~Get Your Files Here !/2 - Building AXI Slave Lite Interface Using Vivado Template without I O ports/5 - Slave Lite Interface without I O Ports P2 Creating IP.mp4 49MB
  26. ~Get Your Files Here !/1 - Section 0 Course Framework/2 - Course Framework.mp4 48MB
  27. ~Get Your Files Here !/12 - AXIS Master Slave Interface with Verilog/65 - Building AXIS Master Slave Interface with Verilog P2.mp4 45MB
  28. ~Get Your Files Here !/3 - Building AXI Slave Lite Interface Using Vivado Template with I O ports/14 - Adding Input and Output ports to Slave Lite Interface P1.mp4 45MB
  29. ~Get Your Files Here !/5 - Adding AXI Lite Interface for existing Verilog Code/26 - Add Existing RTL Delay Generator P2.mp4 44MB
  30. ~Get Your Files Here !/5 - Adding AXI Lite Interface for existing Verilog Code/28 - Adding Existing RTL Multiplier P2.mp4 43MB
  31. ~Get Your Files Here !/7 - Adding Interrupts with Vivado Template/40 - Generating Continuous Interrupt P1.mp4 41MB
  32. ~Get Your Files Here !/2 - Building AXI Slave Lite Interface Using Vivado Template without I O ports/6 - Slave Lite Interface without I O Ports P3 Creating IP.mp4 39MB
  33. ~Get Your Files Here !/2 - Building AXI Slave Lite Interface Using Vivado Template without I O ports/8 - Slave Lite Interface without I O Ports P5 Creating C Application.mp4 38MB
  34. ~Get Your Files Here !/4 - Understanding AXI4-Lite Signals/22 - Block Design used in Demonstration.mp4 38MB
  35. ~Get Your Files Here !/3 - Building AXI Slave Lite Interface Using Vivado Template with I O ports/12 - Adding Output port to Slave Lite Interface P2.mp4 37MB
  36. ~Get Your Files Here !/11 - AXIS Slave Interface with Verilog/59 - Building AXIS Slave Interface with Verilog P1.mp4 37MB
  37. ~Get Your Files Here !/10 - AXI Stream Master Interface with Vivado Template/56 - Creating AXIS Master Interface P2.mp4 35MB
  38. ~Get Your Files Here !/3 - Building AXI Slave Lite Interface Using Vivado Template with I O ports/13 - Adding Output port to Slave Lite Interface P3.mp4 34MB
  39. ~Get Your Files Here !/13 - Understanding Common Errors/69 - Common Error 2.mp4 25MB
  40. ~Get Your Files Here !/4 - Understanding AXI4-Lite Signals/18 - Understanding Mandatory Signal Master Write to Slave (Writing Ops) P1.mp4 25MB
  41. ~Get Your Files Here !/4 - Understanding AXI4-Lite Signals/19 - Understanding Mandatory Signal Master Write to Slave (Writing Ops) P2.mp4 24MB
  42. ~Get Your Files Here !/11 - AXIS Slave Interface with Verilog/61 - Building AXIS Slave Interface with Verilog P3.mp4 23MB
  43. ~Get Your Files Here !/3 - Building AXI Slave Lite Interface Using Vivado Template with I O ports/16 - Adding Input and Output ports to Slave Lite Interface P3.mp4 23MB
  44. ~Get Your Files Here !/7 - Adding Interrupts with Vivado Template/41 - Generating Continuous Interrupt P2.mp4 22MB
  45. ~Get Your Files Here !/13 - Understanding Common Errors/68 - Common Error 1.mp4 19MB
  46. ~Get Your Files Here !/4 - Understanding AXI4-Lite Signals/20 - Understanding Mandatory Signal Master read from Slave (Reading Ops).mp4 12MB
  47. ~Get Your Files Here !/1 - Section 0 Course Framework/1 - Interface Type.mp4 11MB
  48. ~Get Your Files Here !/5 - Adding AXI Lite Interface for existing Verilog Code/24 - Agenda.mp4 5MB
  49. ~Get Your Files Here !/9 - AXI Stream Slave Interface with Vivado Template/48 - Agenda.mp4 3MB
  50. ~Get Your Files Here !/3 - Building AXI Slave Lite Interface Using Vivado Template with I O ports/10 - Agenda.mp4 3MB
  51. ~Get Your Files Here !/12 - AXIS Master Slave Interface with Verilog/63 - Agenda.mp4 2MB
  52. ~Get Your Files Here !/10 - AXI Stream Master Interface with Vivado Template/54 - Agenda.mp4 2MB
  53. ~Get Your Files Here !/4 - Understanding AXI4-Lite Signals/17 - Agenda.mp4 2MB
  54. ~Get Your Files Here !/2 - Building AXI Slave Lite Interface Using Vivado Template without I O ports/3 - Agenda.mp4 2MB
  55. ~Get Your Files Here !/7 - Adding Interrupts with Vivado Template/35 - Agenda.mp4 2MB
  56. ~Get Your Files Here !/8 - Adding Master Interface/44 - Agenda.mp4 2MB
  57. ~Get Your Files Here !/11 - AXIS Slave Interface with Verilog/58 - Agenda.mp4 2MB
  58. ~Get Your Files Here !/6 - Adding Interrupts to Slave Lite Interfaces/30 - Agenda.mp4 2MB
  59. ~Get Your Files Here !/7 - Adding Interrupts with Vivado Template/37 - Using Vivado Interrupt Template Code P2 English.vtt 29KB
  60. ~Get Your Files Here !/9 - AXI Stream Slave Interface with Vivado Template/49 - Building AXIS Slave Interface P1 English.vtt 24KB
  61. ~Get Your Files Here !/10 - AXI Stream Master Interface with Vivado Template/55 - Creating AXIS Master Interface P1 English.vtt 22KB
  62. ~Get Your Files Here !/8 - Adding Master Interface/45 - Creating Master Interface with Vivado Template P1 English.vtt 21KB
  63. ~Get Your Files Here !/7 - Adding Interrupts with Vivado Template/42 - Blinking Effect with Interrupt English.vtt 19KB
  64. ~Get Your Files Here !/7 - Adding Interrupts with Vivado Template/36 - Using Vivado Interrupt Template Code P1 English.vtt 18KB
  65. ~Get Your Files Here !/6 - Adding Interrupts to Slave Lite Interfaces/33 - Adding Interrupt with RTL P2 English.vtt 18KB
  66. ~Get Your Files Here !/12 - AXIS Master Slave Interface with Verilog/64 - Building AXIS Master Slave Interface with Verilog P1 English.vtt 17KB
  67. ~Get Your Files Here !/5 - Adding AXI Lite Interface for existing Verilog Code/25 - Add Existing RTL Delay Generator P1 English.vtt 16KB
  68. ~Get Your Files Here !/4 - Understanding AXI4-Lite Signals/23 - Analyzing Signals on ILA Probe English.vtt 15KB
  69. ~Get Your Files Here !/6 - Adding Interrupts to Slave Lite Interfaces/31 - Fundamentals of Interrupt C Application English.vtt 14KB
  70. ~Get Your Files Here !/6 - Adding Interrupts to Slave Lite Interfaces/32 - Adding Interrupt with RTL P1 English.vtt 14KB
  71. ~Get Your Files Here !/11 - AXIS Slave Interface with Verilog/60 - Building AXIS Slave Interface with Verilog P2 English.vtt 13KB
  72. ~Get Your Files Here !/5 - Adding AXI Lite Interface for existing Verilog Code/27 - Adding Existing RTL Multiplier P1 English.vtt 13KB
  73. ~Get Your Files Here !/4 - Understanding AXI4-Lite Signals/21 - Other Signals in Slave Lite Interface English.vtt 12KB
  74. ~Get Your Files Here !/2 - Building AXI Slave Lite Interface Using Vivado Template without I O ports/7 - Slave Lite Interface without I O Ports P4 Creating C Application English.vtt 11KB
  75. ~Get Your Files Here !/11 - AXIS Slave Interface with Verilog/59 - Building AXIS Slave Interface with Verilog P1 English.vtt 11KB
  76. ~Get Your Files Here !/Building Custom AXI Interface Peripherals for ZYNQ Devices.jpg 11KB
  77. ~Get Your Files Here !/2 - Building AXI Slave Lite Interface Using Vivado Template without I O ports/4 - Slave Lite Interface without I O Ports P1 Creating IP English.vtt 10KB
  78. ~Get Your Files Here !/5 - Adding AXI Lite Interface for existing Verilog Code/29 - Adding Exisitng RTL COMPLEX FSM P1 English.vtt 10KB
  79. ~Get Your Files Here !/9 - AXI Stream Slave Interface with Vivado Template/52 - Building Complex FSM with existing FSM for AXIS English.vtt 10KB
  80. ~Get Your Files Here !/4 - Understanding AXI4-Lite Signals/18 - Understanding Mandatory Signal Master Write to Slave (Writing Ops) P1 English.vtt 9KB
  81. ~Get Your Files Here !/1 - Section 0 Course Framework/2 - Course Framework English.vtt 8KB
  82. ~Get Your Files Here !/7 - Adding Interrupts with Vivado Template/39 - Modifying Delay of the Vivado Interrupt Template English.vtt 8KB
  83. ~Get Your Files Here !/3 - Building AXI Slave Lite Interface Using Vivado Template with I O ports/11 - Adding Output port to Slave Lite Interface P1 English.vtt 8KB
  84. ~Get Your Files Here !/2 - Building AXI Slave Lite Interface Using Vivado Template without I O ports/5 - Slave Lite Interface without I O Ports P2 Creating IP English.vtt 8KB
  85. ~Get Your Files Here !/9 - AXI Stream Slave Interface with Vivado Template/50 - Building AXIS Slave Interface P2 English.vtt 8KB
  86. ~Get Your Files Here !/8 - Adding Master Interface/46 - Creating Master Interface with Vivado Template P2 English.vtt 8KB
  87. ~Get Your Files Here !/3 - Building AXI Slave Lite Interface Using Vivado Template with I O ports/14 - Adding Input and Output ports to Slave Lite Interface P1 English.vtt 8KB
  88. ~Get Your Files Here !/12 - AXIS Master Slave Interface with Verilog/65 - Building AXIS Master Slave Interface with Verilog P2 English.vtt 7KB
  89. ~Get Your Files Here !/4 - Understanding AXI4-Lite Signals/19 - Understanding Mandatory Signal Master Write to Slave (Writing Ops) P2 English.vtt 7KB
  90. ~Get Your Files Here !/Building Custom AXI Interface Peripherals for ZYNQ Devices.txt 6KB
  91. ~Get Your Files Here !/7 - Adding Interrupts with Vivado Template/40 - Generating Continuous Interrupt P1 English.vtt 6KB
  92. ~Get Your Files Here !/5 - Adding AXI Lite Interface for existing Verilog Code/26 - Add Existing RTL Delay Generator P2 English.vtt 6KB
  93. ~Get Your Files Here !/2 - Building AXI Slave Lite Interface Using Vivado Template without I O ports/6 - Slave Lite Interface without I O Ports P3 Creating IP English.vtt 6KB
  94. ~Get Your Files Here !/3 - Building AXI Slave Lite Interface Using Vivado Template with I O ports/15 - Adding Input and Output ports to Slave Lite Interface P2 English.vtt 6KB
  95. ~Get Your Files Here !/4 - Understanding AXI4-Lite Signals/22 - Block Design used in Demonstration English.vtt 5KB
  96. ~Get Your Files Here !/3 - Building AXI Slave Lite Interface Using Vivado Template with I O ports/12 - Adding Output port to Slave Lite Interface P2 English.vtt 5KB
  97. ~Get Your Files Here !/10 - AXI Stream Master Interface with Vivado Template/56 - Creating AXIS Master Interface P2 English.vtt 5KB
  98. ~Get Your Files Here !/2 - Building AXI Slave Lite Interface Using Vivado Template without I O ports/8 - Slave Lite Interface without I O Ports P5 Creating C Application English.vtt 5KB
  99. ~Get Your Files Here !/5 - Adding AXI Lite Interface for existing Verilog Code/28 - Adding Existing RTL Multiplier P2 English.vtt 5KB
  100. ~Get Your Files Here !/11 - AXIS Slave Interface with Verilog/61 - Building AXIS Slave Interface with Verilog P3 English.vtt 5KB
  101. ~Get Your Files Here !/3 - Building AXI Slave Lite Interface Using Vivado Template with I O ports/13 - Adding Output port to Slave Lite Interface P3 English.vtt 4KB
  102. ~Get Your Files Here !/13 - Understanding Common Errors/69 - Common Error 2 English.vtt 4KB
  103. ~Get Your Files Here !/4 - Understanding AXI4-Lite Signals/20 - Understanding Mandatory Signal Master read from Slave (Reading Ops) English.vtt 4KB
  104. ~Get Your Files Here !/9 - AXI Stream Slave Interface with Vivado Template/53 - Code.html 3KB
  105. ~Get Your Files Here !/13 - Understanding Common Errors/68 - Common Error 1 English.vtt 3KB
  106. ~Get Your Files Here !/3 - Building AXI Slave Lite Interface Using Vivado Template with I O ports/16 - Adding Input and Output ports to Slave Lite Interface P3 English.vtt 3KB
  107. ~Get Your Files Here !/7 - Adding Interrupts with Vivado Template/41 - Generating Continuous Interrupt P2 English.vtt 3KB
  108. ~Get Your Files Here !/12 - AXIS Master Slave Interface with Verilog/67 - Code and BD.html 3KB
  109. ~Get Your Files Here !/7 - Adding Interrupts with Vivado Template/43 - Code.html 2KB
  110. ~Get Your Files Here !/11 - AXIS Slave Interface with Verilog/62 - Code and BD.html 2KB
  111. ~Get Your Files Here !/6 - Adding Interrupts to Slave Lite Interfaces/34 - Code.html 2KB
  112. ~Get Your Files Here !/12 - AXIS Master Slave Interface with Verilog/66 - Code and BD.html 2KB
  113. ~Get Your Files Here !/1 - Section 0 Course Framework/1 - Interface Type English.vtt 2KB
  114. ~Get Your Files Here !/7 - Adding Interrupts with Vivado Template/38 - Code.html 2KB
  115. ~Get Your Files Here !/5 - Adding AXI Lite Interface for existing Verilog Code/24 - Agenda English.vtt 1KB
  116. ~Get Your Files Here !/10 - AXI Stream Master Interface with Vivado Template/57 - Code.html 1KB
  117. ~Get Your Files Here !/9 - AXI Stream Slave Interface with Vivado Template/48 - Agenda English.vtt 974B
  118. ~Get Your Files Here !/4 - Understanding AXI4-Lite Signals/17 - Agenda English.vtt 964B
  119. ~Get Your Files Here !/7 - Adding Interrupts with Vivado Template/35 - Agenda English.vtt 945B
  120. ~Get Your Files Here !/12 - AXIS Master Slave Interface with Verilog/63 - Agenda English.vtt 917B
  121. ~Get Your Files Here !/6 - Adding Interrupts to Slave Lite Interfaces/30 - Agenda English.vtt 899B
  122. ~Get Your Files Here !/8 - Adding Master Interface/44 - Agenda English.vtt 792B
  123. ~Get Your Files Here !/2 - Building AXI Slave Lite Interface Using Vivado Template without I O ports/9 - C Code.html 791B
  124. ~Get Your Files Here !/10 - AXI Stream Master Interface with Vivado Template/54 - Agenda English.vtt 775B
  125. ~Get Your Files Here !/9 - AXI Stream Slave Interface with Vivado Template/51 - Code.html 775B
  126. ~Get Your Files Here !/3 - Building AXI Slave Lite Interface Using Vivado Template with I O ports/10 - Agenda English.vtt 746B
  127. ~Get Your Files Here !/11 - AXIS Slave Interface with Verilog/58 - Agenda English.vtt 613B
  128. ~Get Your Files Here !/2 - Building AXI Slave Lite Interface Using Vivado Template without I O ports/3 - Agenda English.vtt 583B
  129. ~Get Your Files Here !/8 - Adding Master Interface/47 - Code.html 576B
  130. ~Get Your Files Here !/Bonus Resources.txt 386B
  131. Get Bonus Downloads Here.url 182B