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[ ] Udemy - VSD - Custom Layout

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  • 文件大小:591MB
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文件列表

  1. ~Get Your Files Here !/06 - Art of layout using Euler's path plus Stick diagram/009 Final layout and inputoutput labelling.mp4 51MB
  2. ~Get Your Files Here !/05 - Introduction to euler's path and stick diagram/003 Derive actual dimension from stick diagram.mp4 41MB
  3. ~Get Your Files Here !/04 - Design rule checking (DRC)/002 Poly extension and poly to diffusion spacing rules.mp4 26MB
  4. ~Get Your Files Here !/04 - Design rule checking (DRC)/005 Contact spacing and minimum active width rules.mp4 25MB
  5. ~Get Your Files Here !/06 - Art of layout using Euler's path plus Stick diagram/006 Derive actual dimension for Fn.mp4 25MB
  6. ~Get Your Files Here !/06 - Art of layout using Euler's path plus Stick diagram/007 Script to create layout.mp4 23MB
  7. ~Get Your Files Here !/04 - Design rule checking (DRC)/001 Introduction to DRC and lambda design rules.mp4 22MB
  8. ~Get Your Files Here !/06 - Art of layout using Euler's path plus Stick diagram/005 Abstract layout from stick diagram.mp4 21MB
  9. ~Get Your Files Here !/04 - Design rule checking (DRC)/003 Poly to diffusion spacing and diffusion contact width rules.mp4 21MB
  10. ~Get Your Files Here !/03 - Introduction to ‘corner stitching’ and ‘tech files’/003 Corner stitching introduction.mp4 20MB
  11. ~Get Your Files Here !/03 - Introduction to ‘corner stitching’ and ‘tech files’/005 Active tile types and tech file content.mp4 19MB
  12. ~Get Your Files Here !/04 - Design rule checking (DRC)/006 From logic to layout to SPICE.mp4 19MB
  13. ~Get Your Files Here !/05 - Introduction to euler's path and stick diagram/002 Introduction to stick diagram.mp4 19MB
  14. ~Get Your Files Here !/03 - Introduction to ‘corner stitching’ and ‘tech files’/007 Connect section for circuit extraction.mp4 18MB
  15. ~Get Your Files Here !/06 - Art of layout using Euler's path plus Stick diagram/001 Pre-layout simulation.mp4 18MB
  16. ~Get Your Files Here !/06 - Art of layout using Euler's path plus Stick diagram/002 Layout using 'only' stick diagram.mp4 17MB
  17. ~Get Your Files Here !/05 - Introduction to euler's path and stick diagram/001 Introduction to simple path, euler's path and euler's circuit.mp4 17MB
  18. ~Get Your Files Here !/02 - Inception of layout - CMOS fabrication process/001 Create active regions.mp4 17MB
  19. ~Get Your Files Here !/07 - Conclusion, acknowledgements and what next!!!/003 Post-layout simulation and conclusion.mp4 16MB
  20. ~Get Your Files Here !/03 - Introduction to ‘corner stitching’ and ‘tech files’/004 Corner stitch to planes to tiles.mp4 16MB
  21. ~Get Your Files Here !/02 - Inception of layout - CMOS fabrication process/007 Higher level metal formation.mp4 16MB
  22. ~Get Your Files Here !/03 - Introduction to ‘corner stitching’ and ‘tech files’/006 Contacts and styles.mp4 16MB
  23. ~Get Your Files Here !/06 - Art of layout using Euler's path plus Stick diagram/004 Improved stick diagram for new gate input ordering.mp4 15MB
  24. ~Get Your Files Here !/04 - Design rule checking (DRC)/004 Metal1 width and poly to metal1 spacing rules.mp4 15MB
  25. ~Get Your Files Here !/02 - Inception of layout - CMOS fabrication process/003 Formation of gate terminal.mp4 14MB
  26. ~Get Your Files Here !/06 - Art of layout using Euler's path plus Stick diagram/003 Euler's path for Fn - Input gate ordering.mp4 13MB
  27. ~Get Your Files Here !/02 - Inception of layout - CMOS fabrication process/004 Lightly doped drain (LDD) formation.mp4 12MB
  28. ~Get Your Files Here !/02 - Inception of layout - CMOS fabrication process/006 Local interconnect formation.mp4 11MB
  29. ~Get Your Files Here !/02 - Inception of layout - CMOS fabrication process/002 Formation of N-well and P-well.mp4 11MB
  30. ~Get Your Files Here !/02 - Inception of layout - CMOS fabrication process/005 Source drain formation.mp4 8MB
  31. ~Get Your Files Here !/01 - Introduction/001 Course content.mp4 7MB
  32. ~Get Your Files Here !/06 - Art of layout using Euler's path plus Stick diagram/006 Derive actual dimension for Fn_en.vtt 15KB
  33. ~Get Your Files Here !/05 - Introduction to euler's path and stick diagram/002 Introduction to stick diagram_en.vtt 15KB
  34. ~Get Your Files Here !/04 - Design rule checking (DRC)/002 Poly extension and poly to diffusion spacing rules_en.vtt 14KB
  35. ~Get Your Files Here !/06 - Art of layout using Euler's path plus Stick diagram/005 Abstract layout from stick diagram_en.vtt 14KB
  36. ~Get Your Files Here !/05 - Introduction to euler's path and stick diagram/001 Introduction to simple path, euler's path and euler's circuit_en.vtt 14KB
  37. ~Get Your Files Here !/06 - Art of layout using Euler's path plus Stick diagram/002 Layout using 'only' stick diagram_en.vtt 14KB
  38. ~Get Your Files Here !/06 - Art of layout using Euler's path plus Stick diagram/007 Script to create layout_en.vtt 14KB
  39. ~Get Your Files Here !/03 - Introduction to ‘corner stitching’ and ‘tech files’/003 Corner stitching introduction_en.vtt 14KB
  40. ~Get Your Files Here !/05 - Introduction to euler's path and stick diagram/003 Derive actual dimension from stick diagram_en.vtt 14KB
  41. ~Get Your Files Here !/06 - Art of layout using Euler's path plus Stick diagram/009 Final layout and inputoutput labelling_en.vtt 14KB
  42. ~Get Your Files Here !/03 - Introduction to ‘corner stitching’ and ‘tech files’/005 Active tile types and tech file content_en.vtt 14KB
  43. ~Get Your Files Here !/02 - Inception of layout - CMOS fabrication process/001 Create active regions_en.vtt 14KB
  44. ~Get Your Files Here !/03 - Introduction to ‘corner stitching’ and ‘tech files’/007 Connect section for circuit extraction_en.vtt 14KB
  45. ~Get Your Files Here !/04 - Design rule checking (DRC)/001 Introduction to DRC and lambda design rules_en.vtt 13KB
  46. ~Get Your Files Here !/06 - Art of layout using Euler's path plus Stick diagram/001 Pre-layout simulation_en.vtt 13KB
  47. ~Get Your Files Here !/02 - Inception of layout - CMOS fabrication process/007 Higher level metal formation_en.vtt 13KB
  48. ~Get Your Files Here !/06 - Art of layout using Euler's path plus Stick diagram/004 Improved stick diagram for new gate input ordering_en.vtt 13KB
  49. ~Get Your Files Here !/02 - Inception of layout - CMOS fabrication process/003 Formation of gate terminal_en.vtt 12KB
  50. ~Get Your Files Here !/04 - Design rule checking (DRC)/003 Poly to diffusion spacing and diffusion contact width rules_en.vtt 12KB
  51. ~Get Your Files Here !/03 - Introduction to ‘corner stitching’ and ‘tech files’/006 Contacts and styles_en.vtt 12KB
  52. ~Get Your Files Here !/04 - Design rule checking (DRC)/006 From logic to layout to SPICE_en.vtt 11KB
  53. ~Get Your Files Here !/04 - Design rule checking (DRC)/005 Contact spacing and minimum active width rules_en.vtt 11KB
  54. ~Get Your Files Here !/03 - Introduction to ‘corner stitching’ and ‘tech files’/004 Corner stitch to planes to tiles_en.vtt 11KB
  55. ~Get Your Files Here !/06 - Art of layout using Euler's path plus Stick diagram/003 Euler's path for Fn - Input gate ordering_en.vtt 11KB
  56. ~Get Your Files Here !/02 - Inception of layout - CMOS fabrication process/004 Lightly doped drain (LDD) formation_en.vtt 10KB
  57. ~Get Your Files Here !/02 - Inception of layout - CMOS fabrication process/006 Local interconnect formation_en.vtt 10KB
  58. ~Get Your Files Here !/07 - Conclusion, acknowledgements and what next!!!/003 Post-layout simulation and conclusion_en.vtt 10KB
  59. ~Get Your Files Here !/02 - Inception of layout - CMOS fabrication process/002 Formation of N-well and P-well_en.vtt 9KB
  60. ~Get Your Files Here !/04 - Design rule checking (DRC)/004 Metal1 width and poly to metal1 spacing rules_en.vtt 8KB
  61. ~Get Your Files Here !/03 - Introduction to ‘corner stitching’ and ‘tech files’/002 min2.tech.html 8KB
  62. ~Get Your Files Here !/01 - Introduction/001 Course content_en.vtt 7KB
  63. ~Get Your Files Here !/02 - Inception of layout - CMOS fabrication process/005 Source drain formation_en.vtt 6KB
  64. ~Get Your Files Here !/07 - Conclusion, acknowledgements and what next!!!/002 fn_postlayout.mag.html 3KB
  65. ~Get Your Files Here !/06 - Art of layout using Euler's path plus Stick diagram/008 draw_fn.tcl.html 3KB
  66. ~Get Your Files Here !/03 - Introduction to ‘corner stitching’ and ‘tech files’/001 INV.mag.html 1KB
  67. ~Get Your Files Here !/07 - Conclusion, acknowledgements and what next!!!/001 fn_prelayout.cir.html 946B
  68. ~Get Your Files Here !/Bonus Resources.txt 386B
  69. Get Bonus Downloads Here.url 181B