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[ ] Udemy - Verilog HDL Fundamentals for Digital Design and Verification

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文件列表

  1. ~Get Your Files Here !/12. Verilog Design Examples/5. Action Time - Design a Stream Cypher.mp4 113MB
  2. ~Get Your Files Here !/12. Verilog Design Examples/3. Action Time - Data Transfer FSM.mp4 109MB
  3. ~Get Your Files Here !/11. Verilog State Machines/3. Action Time - Special Semaphore (Mealy FSM).mp4 103MB
  4. ~Get Your Files Here !/12. Verilog Design Examples/2. Action Time - Synchronous FIFO.mp4 78MB
  5. ~Get Your Files Here !/11. Verilog State Machines/2. Action Time - Metro turnstile (Mealy FSM).mp4 70MB
  6. ~Get Your Files Here !/9. Verilog Functions and Tasks/14. Action Time - ALU self-checking testbench.mp4 59MB
  7. ~Get Your Files Here !/10. Verilog Memory Design/2. Action Time - Single Port Async Read SRAM.mp4 51MB
  8. ~Get Your Files Here !/7. Verilog Combinational Design/25. Action time - Design an Arithmetical Logical Unit (ALU).mp4 51MB
  9. ~Get Your Files Here !/1. Introduction/2. Course overview.mp4 50MB
  10. ~Get Your Files Here !/10. Verilog Memory Design/4. Action Time - Dual Port Async Read SRAM.mp4 50MB
  11. ~Get Your Files Here !/1. Introduction/1. Welcome!.mp4 44MB
  12. ~Get Your Files Here !/8. Verilog Sequential Design/7. Action Time - D_Flip_Flop_sync_rstn.mp4 42MB
  13. ~Get Your Files Here !/8. Verilog Sequential Design/14. Action Time - Shift_Reg_PISO.mp4 40MB
  14. ~Get Your Files Here !/9. Verilog Functions and Tasks/12. Action Time - Shift Reg PIPO buggy.mp4 40MB
  15. ~Get Your Files Here !/8. Verilog Sequential Design/17. Action Time - Linear Feedback Shift Register.mp4 39MB
  16. ~Get Your Files Here !/8. Verilog Sequential Design/15. Action Time - Shift_Left_Right_Reg.mp4 39MB
  17. ~Get Your Files Here !/10. Verilog Memory Design/5. Action Time - Single Port Sync Read ROM.mp4 38MB
  18. ~Get Your Files Here !/8. Verilog Sequential Design/20. Action Time - Nbit updown Counter.mp4 37MB
  19. ~Get Your Files Here !/8. Verilog Sequential Design/24. Action Time - Clock Divider by 3.mp4 37MB
  20. ~Get Your Files Here !/5. Verilog Design Styles/6. Verilog_Behavioral_style.mp4 36MB
  21. ~Get Your Files Here !/4. Verilog Module/1. Verilog Module - the basics.mp4 35MB
  22. ~Get Your Files Here !/5. Verilog Design Styles/15. Action Time - 4bit_full_adder structural.mp4 34MB
  23. ~Get Your Files Here !/11. Verilog State Machines/1. Discover Finite State Machines.mp4 34MB
  24. ~Get Your Files Here !/8. Verilog Sequential Design/12. Action Time - Shift_Reg_SIPO.mp4 34MB
  25. ~Get Your Files Here !/7. Verilog Combinational Design/23. Action Time - HEX 7segment decoder.mp4 32MB
  26. ~Get Your Files Here !/8. Verilog Sequential Design/21. Action Time - Modulo_N Counter.mp4 32MB
  27. ~Get Your Files Here !/11. Verilog State Machines/5. Action Time - Sequence Detector NON Overlaping.mp4 31MB
  28. ~Get Your Files Here !/1. Introduction/4. Understand Abstraction Levels.mp4 31MB
  29. ~Get Your Files Here !/8. Verilog Sequential Design/2. Action Time - Clocks Generator.mp4 29MB
  30. ~Get Your Files Here !/4. Verilog Module/2. Action time - Do your first testbench.mp4 29MB
  31. ~Get Your Files Here !/7. Verilog Combinational Design/21. Action Time - demux_4x_nbit.mp4 29MB
  32. ~Get Your Files Here !/7. Verilog Combinational Design/13. Action Time - 4to16 binary Decoder.mp4 29MB
  33. ~Get Your Files Here !/9. Verilog Functions and Tasks/7. Action Time - Nbit Comparator Function.mp4 28MB
  34. ~Get Your Files Here !/11. Verilog State Machines/7. Verilog Mealy FSM Template.mp4 28MB
  35. ~Get Your Files Here !/8. Verilog Sequential Design/6. Basics of edge-triggered logic.mp4 28MB
  36. ~Get Your Files Here !/10. Verilog Memory Design/1. Basics of Semiconductor Memory.mp4 27MB
  37. ~Get Your Files Here !/8. Verilog Sequential Design/11. Action Time - Shift_Reg_PIPO.mp4 26MB
  38. ~Get Your Files Here !/12. Verilog Design Examples/4. Basics of Data Ecryption.mp4 26MB
  39. ~Get Your Files Here !/8. Verilog Sequential Design/1. Sequential Logic Basics.mp4 25MB
  40. ~Get Your Files Here !/7. Verilog Combinational Design/22. Master the Seven Segment Display Decoder.mp4 25MB
  41. ~Get Your Files Here !/10. Verilog Memory Design/3. Action Time - Single Port Sync Read SRAM.mp4 25MB
  42. ~Get Your Files Here !/8. Verilog Sequential Design/19. Action Time - Nbit Counter.mp4 23MB
  43. ~Get Your Files Here !/7. Verilog Combinational Design/14. Action Time - 8to3 Encoder.mp4 23MB
  44. ~Get Your Files Here !/12. Verilog Design Examples/1. Discover the First In First Out (FIFO) circuit.mp4 23MB
  45. ~Get Your Files Here !/8. Verilog Sequential Design/23. Action Time - Clock Divider Nbit.mp4 23MB
  46. ~Get Your Files Here !/7. Verilog Combinational Design/19. Action Time - mux_4x_nbit.mp4 23MB
  47. ~Get Your Files Here !/7. Verilog Combinational Design/9. Action Time - Nbit Comparator.mp4 23MB
  48. ~Get Your Files Here !/7. Verilog Combinational Design/11. Action Time - Nbit Decoder.mp4 23MB
  49. ~Get Your Files Here !/3. Verilog Data Types and Operators/8. Action time - Vectors.mp4 22MB
  50. ~Get Your Files Here !/5. Verilog Design Styles/3. Action Time - half adder structural.mp4 22MB
  51. ~Get Your Files Here !/6. Verilog Structural Design/4. Discover the Multiplexer.mp4 22MB
  52. ~Get Your Files Here !/8. Verilog Sequential Design/10. Discover the Shift Register.mp4 22MB
  53. ~Get Your Files Here !/7. Verilog Combinational Design/8. Action Time - Nbit Adder.mp4 22MB
  54. ~Get Your Files Here !/9. Verilog Functions and Tasks/1. Verilog Functions Basics.mp4 22MB
  55. ~Get Your Files Here !/1. Introduction/5. Discover the Modern Digital Design Flow.mp4 21MB
  56. ~Get Your Files Here !/6. Verilog Structural Design/13. Action Time - 1bit_comparator.mp4 21MB
  57. ~Get Your Files Here !/8. Verilog Sequential Design/13. Action Time - Shift_Reg_SISO.mp4 20MB
  58. ~Get Your Files Here !/7. Verilog Combinational Design/24. How to use digital logic for arithmetic operations.mp4 20MB
  59. ~Get Your Files Here !/8. Verilog Sequential Design/18. Discover Synchronous Counters.mp4 20MB
  60. ~Get Your Files Here !/2. Install the Simulator/2. Install Intel Quartus Prime Lite and Modelsim.mp4 20MB
  61. ~Get Your Files Here !/9. Verilog Functions and Tasks/13. Discover Automated Verification.mp4 20MB
  62. ~Get Your Files Here !/7. Verilog Combinational Design/4. Action Time - Adder Tree.mp4 20MB
  63. ~Get Your Files Here !/8. Verilog Sequential Design/22. Discover Digital Frequency Dividers.mp4 19MB
  64. ~Get Your Files Here !/7. Verilog Combinational Design/1. What is Combinational logic.mp4 19MB
  65. ~Get Your Files Here !/3. Verilog Data Types and Operators/6. Action time - Literal values.mp4 19MB
  66. ~Get Your Files Here !/7. Verilog Combinational Design/5. Discover Procedural Assignments.mp4 19MB
  67. ~Get Your Files Here !/9. Verilog Functions and Tasks/10. Action Time - Verilog Tasks Control Shift Reg.mp4 19MB
  68. ~Get Your Files Here !/8. Verilog Sequential Design/3. Types of Sequential Digital Logic.mp4 19MB
  69. ~Get Your Files Here !/6. Verilog Structural Design/7. Action Time -1bit_demux.mp4 19MB
  70. ~Get Your Files Here !/6. Verilog Structural Design/2. Verilog Built-in_Primitives.mp4 19MB
  71. ~Get Your Files Here !/5. Verilog Design Styles/13. Action Time - full_adder behavioral.mp4 19MB
  72. ~Get Your Files Here !/2. Install the Simulator/3. Action Time - Hello World using Verilog.mp4 18MB
  73. ~Get Your Files Here !/5. Verilog Design Styles/5. Action Time - half_adder dataflow.mp4 18MB
  74. ~Get Your Files Here !/7. Verilog Combinational Design/17. Action Time - Priority Encoder2 4to2.mp4 18MB
  75. ~Get Your Files Here !/5. Verilog Design Styles/11. Action Time - full_adder structural.mp4 18MB
  76. ~Get Your Files Here !/7. Verilog Combinational Design/16. Action Time - Priority Encoder1 4to2.mp4 18MB
  77. ~Get Your Files Here !/2. Install the Simulator/1. Discover the Verilog Simulation.mp4 18MB
  78. ~Get Your Files Here !/8. Verilog Sequential Design/4. Action Time - The D_Latch.mp4 17MB
  79. ~Get Your Files Here !/5. Verilog Design Styles/16. Action Time - 4bit_full_adder dataflow.mp4 17MB
  80. ~Get Your Files Here !/1. Introduction/3. What is Verilog HDL.mp4 17MB
  81. ~Get Your Files Here !/3. Verilog Data Types and Operators/4. Action time - Multiple procedures.mp4 17MB
  82. ~Get Your Files Here !/7. Verilog Combinational Design/15. What is a Priority Encoder.mp4 17MB
  83. ~Get Your Files Here !/3. Verilog Data Types and Operators/29. Action Time - Replication Operator.mp4 17MB
  84. ~Get Your Files Here !/6. Verilog Structural Design/5. Action Time - 1bit_mux.mp4 17MB
  85. ~Get Your Files Here !/8. Verilog Sequential Design/5. Action Time - D_Latch_reset_n.mp4 16MB
  86. ~Get Your Files Here !/12. Verilog Design Examples/6. Congratulations!.mp4 16MB
  87. ~Get Your Files Here !/7. Verilog Combinational Design/6. Action Time - Tree Adder Procedural.mp4 16MB
  88. ~Get Your Files Here !/4. Verilog Module/6. Action Time - Generate Waveforms.mp4 16MB
  89. ~Get Your Files Here !/9. Verilog Functions and Tasks/5. Action Time - Verilog Functions Factorial.mp4 16MB
  90. ~Get Your Files Here !/3. Verilog Data Types and Operators/3. Hardware Description Language data types.mp4 16MB
  91. ~Get Your Files Here !/8. Verilog Sequential Design/8. Action Time - D_Flip_Flop_async_rstn.mp4 16MB
  92. ~Get Your Files Here !/8. Verilog Sequential Design/16. Discover the Linear Feedback Shift Register.mp4 15MB
  93. ~Get Your Files Here !/6. Verilog Structural Design/6. Discover the Demultiplexer.mp4 15MB
  94. ~Get Your Files Here !/7. Verilog Combinational Design/10. Differentiate between binary encoders and decoders.mp4 15MB
  95. ~Get Your Files Here !/3. Verilog Data Types and Operators/1. Verilog Data types overview.mp4 15MB
  96. ~Get Your Files Here !/9. Verilog Functions and Tasks/4. Discover Verilog Recursive Functions.mp4 15MB
  97. ~Get Your Files Here !/3. Verilog Data Types and Operators/15. Action Time - Logical Operators usage.mp4 15MB
  98. ~Get Your Files Here !/6. Verilog Structural Design/11. Action Time - mux_tri-state.mp4 15MB
  99. ~Get Your Files Here !/3. Verilog Data Types and Operators/2. Action time - sum and product.mp4 15MB
  100. ~Get Your Files Here !/5. Verilog Design Styles/10. Design a 1bit full_adder.mp4 15MB
  101. ~Get Your Files Here !/5. Verilog Design Styles/8. Action Time - Initial Procedures.mp4 14MB
  102. ~Get Your Files Here !/7. Verilog Combinational Design/3. Action Time - Continuous assignments.mp4 14MB
  103. ~Get Your Files Here !/9. Verilog Functions and Tasks/11. Why our code looks like software.mp4 14MB
  104. ~Get Your Files Here !/3. Verilog Data Types and Operators/12. Action Time - Reduction operators.mp4 14MB
  105. ~Get Your Files Here !/3. Verilog Data Types and Operators/27. Action Time - Concatenation Operator.mp4 14MB
  106. ~Get Your Files Here !/3. Verilog Data Types and Operators/10. Action Time - Bit-wise operators.mp4 14MB
  107. ~Get Your Files Here !/5. Verilog Design Styles/1. What are HDL Design Styles.mp4 14MB
  108. ~Get Your Files Here !/5. Verilog Design Styles/9. Action Time - half_adder behavioral.mp4 13MB
  109. ~Get Your Files Here !/3. Verilog Data Types and Operators/31. Action Time - Operators Precedence.mp4 13MB
  110. ~Get Your Files Here !/9. Verilog Functions and Tasks/2. Action Time - Verilog Functions1.mp4 13MB
  111. ~Get Your Files Here !/3. Verilog Data Types and Operators/5. What are Literal Values.mp4 12MB
  112. ~Get Your Files Here !/3. Verilog Data Types and Operators/25. Action Time - Conditional Operator.mp4 12MB
  113. ~Get Your Files Here !/7. Verilog Combinational Design/18. Discover bus Multiplexers.mp4 12MB
  114. ~Get Your Files Here !/3. Verilog Data Types and Operators/9. Verilog Operators - Bit-wise.mp4 12MB
  115. ~Get Your Files Here !/11. Verilog State Machines/6. Action Time - Sequence Detector Overlaping.mp4 12MB
  116. ~Get Your Files Here !/3. Verilog Data Types and Operators/18. Verilog Operators - Shift.mp4 12MB
  117. ~Get Your Files Here !/3. Verilog Data Types and Operators/19. Action Time - Shift Operators.mp4 12MB
  118. ~Get Your Files Here !/8. Verilog Sequential Design/9. Remember!.mp4 11MB
  119. ~Get Your Files Here !/5. Verilog Design Styles/17. Action Time - 4bit_full_adder behavioral.mp4 11MB
  120. ~Get Your Files Here !/9. Verilog Functions and Tasks/6. Action Time - Verilog Functions Fibonacci.mp4 11MB
  121. ~Get Your Files Here !/5. Verilog Design Styles/12. Action Time - full_adder dataflow.mp4 11MB
  122. ~Get Your Files Here !/9. Verilog Functions and Tasks/9. Action Time - Verilog Tasks Distance Conversion.mp4 11MB
  123. ~Get Your Files Here !/2. Install the Simulator/4. Congratulations!.mp4 11MB
  124. ~Get Your Files Here !/7. Verilog Combinational Design/2. Discover Continuous assignments.mp4 11MB
  125. ~Get Your Files Here !/11. Verilog State Machines/4. Basics of Sequence Detectors.mp4 10MB
  126. ~Get Your Files Here !/6. Verilog Structural Design/9. Action Time - tri-state_buffer.mp4 10MB
  127. ~Get Your Files Here !/3. Verilog Data Types and Operators/21. Action Time - Relational Operators.mp4 10MB
  128. ~Get Your Files Here !/3. Verilog Data Types and Operators/7. Vectors in Verilog.mp4 10MB
  129. ~Get Your Files Here !/4. Verilog Module/5. Discover Time and Waveforms.mp4 10MB
  130. ~Get Your Files Here !/5. Verilog Design Styles/2. Verilog Structural Design.mp4 10MB
  131. ~Get Your Files Here !/9. Verilog Functions and Tasks/3. Action Time - Verilog Functions2.mp4 10MB
  132. ~Get Your Files Here !/3. Verilog Data Types and Operators/14. Action Time - Logical Operators.mp4 10MB
  133. ~Get Your Files Here !/3. Verilog Data Types and Operators/22. Verilog Operators - Equality.mp4 10MB
  134. ~Get Your Files Here !/9. Verilog Functions and Tasks/8. Verilog Tasks Basics.mp4 10MB
  135. ~Get Your Files Here !/6. Verilog Structural Design/3. Action Time - Built-in_gates.mp4 10MB
  136. ~Get Your Files Here !/5. Verilog Design Styles/14. Design a 4bit full_adder.mp4 10MB
  137. ~Get Your Files Here !/3. Verilog Data Types and Operators/28. Verilog Operators - Replication.mp4 9MB
  138. ~Get Your Files Here !/6. Verilog Structural Design/10. How to implement a multiplexer using tri-state buffers.mp4 9MB
  139. ~Get Your Files Here !/7. Verilog Combinational Design/12. How to use multiple binary decoders.mp4 9MB
  140. ~Get Your Files Here !/6. Verilog Structural Design/1. What is Structural Design.mp4 9MB
  141. ~Get Your Files Here !/4. Verilog Module/4. What is a Testbench Architecture.mp4 9MB
  142. ~Get Your Files Here !/7. Verilog Combinational Design/20. Discover bus Demultiplexers.mp4 9MB
  143. ~Get Your Files Here !/5. Verilog Design Styles/18. Congratulations!.mp4 9MB
  144. ~Get Your Files Here !/6. Verilog Structural Design/8. The Tri-state buffer.mp4 8MB
  145. ~Get Your Files Here !/6. Verilog Structural Design/14. Remember!.mp4 8MB
  146. ~Get Your Files Here !/3. Verilog Data Types and Operators/13. Verilog Operators - Logical.mp4 8MB
  147. ~Get Your Files Here !/4. Verilog Module/3. Remember!.mp4 8MB
  148. ~Get Your Files Here !/3. Verilog Data Types and Operators/17. Action Time - Arithmetic Operators.mp4 7MB
  149. ~Get Your Files Here !/7. Verilog Combinational Design/7. Discover the Nbit Adder.mp4 7MB
  150. ~Get Your Files Here !/5. Verilog Design Styles/4. Verilog Dataflow style.mp4 7MB
  151. ~Get Your Files Here !/7. Verilog Combinational Design/26. Remember!.mp4 7MB
  152. ~Get Your Files Here !/3. Verilog Data Types and Operators/23. Action Time - Equality Operators.mp4 7MB
  153. ~Get Your Files Here !/5. Verilog Design Styles/7. Remember!.mp4 7MB
  154. ~Get Your Files Here !/3. Verilog Data Types and Operators/24. Verilog Operators - Conditional.mp4 7MB
  155. ~Get Your Files Here !/3. Verilog Data Types and Operators/32. Congratulations!.mp4 6MB
  156. ~Get Your Files Here !/3. Verilog Data Types and Operators/26. Verilog Operators - Concatenation.mp4 6MB
  157. ~Get Your Files Here !/3. Verilog Data Types and Operators/20. Verilog Operators - Relational.mp4 6MB
  158. ~Get Your Files Here !/6. Verilog Structural Design/12. Discover the 1bit Comparator.mp4 6MB
  159. ~Get Your Files Here !/3. Verilog Data Types and Operators/30. Verilog Operators - Precedence.mp4 5MB
  160. ~Get Your Files Here !/3. Verilog Data Types and Operators/11. Verilog Operators - Reduction.mp4 4MB
  161. ~Get Your Files Here !/3. Verilog Data Types and Operators/16. Verilog Operators - Arithmetic.mp4 4MB
  162. ~Get Your Files Here !/12. Verilog Design Examples/5. Action Time - Design a Stream Cypher.srt 15KB
  163. ~Get Your Files Here !/12. Verilog Design Examples/3. Action Time - Data Transfer FSM.srt 14KB
  164. ~Get Your Files Here !/11. Verilog State Machines/3. Action Time - Special Semaphore (Mealy FSM).srt 14KB
  165. ~Get Your Files Here !/7. Verilog Combinational Design/14.1 encoder_8to3.v 11KB
  166. ~Get Your Files Here !/8. Verilog Sequential Design/11.1 shift_reg_pipo.v 11KB
  167. ~Get Your Files Here !/7. Verilog Combinational Design/17.1 prio_enc2_4to2.v 11KB
  168. ~Get Your Files Here !/3. Verilog Data Types and Operators/4.1 easy_verilog_example.v 11KB
  169. ~Get Your Files Here !/12. Verilog Design Examples/2. Action Time - Synchronous FIFO.srt 10KB
  170. ~Get Your Files Here !/11. Verilog State Machines/2. Action Time - Metro turnstile (Mealy FSM).srt 10KB
  171. ~Get Your Files Here !/9. Verilog Functions and Tasks/14.1 ALU.v 7KB
  172. ~Get Your Files Here !/9. Verilog Functions and Tasks/14. Action Time - ALU self-checking testbench.srt 7KB
  173. ~Get Your Files Here !/7. Verilog Combinational Design/25. Action time - Design an Arithmetical Logical Unit (ALU).srt 7KB
  174. ~Get Your Files Here !/10. Verilog Memory Design/4. Action Time - Dual Port Async Read SRAM.srt 7KB
  175. ~Get Your Files Here !/10. Verilog Memory Design/2. Action Time - Single Port Async Read SRAM.srt 6KB
  176. ~Get Your Files Here !/8. Verilog Sequential Design/14. Action Time - Shift_Reg_PISO.srt 6KB
  177. ~Get Your Files Here !/8. Verilog Sequential Design/7. Action Time - D_Flip_Flop_sync_rstn.srt 6KB
  178. ~Get Your Files Here !/8. Verilog Sequential Design/17. Action Time - Linear Feedback Shift Register.srt 5KB
  179. ~Get Your Files Here !/8. Verilog Sequential Design/15. Action Time - Shift_Left_Right_Reg.srt 5KB
  180. ~Get Your Files Here !/9. Verilog Functions and Tasks/12. Action Time - Shift Reg PIPO buggy.srt 5KB
  181. ~Get Your Files Here !/1. Introduction/2. Course overview.srt 5KB
  182. ~Get Your Files Here !/8. Verilog Sequential Design/20. Action Time - Nbit updown Counter.srt 5KB
  183. ~Get Your Files Here !/10. Verilog Memory Design/5. Action Time - Single Port Sync Read ROM.srt 5KB
  184. ~Get Your Files Here !/8. Verilog Sequential Design/24. Action Time - Clock Divider by 3.srt 5KB
  185. ~Get Your Files Here !/10. Verilog Memory Design/4.1 ram_dp_async_read.v 4KB
  186. ~Get Your Files Here !/1. Introduction/1. Welcome!.srt 4KB
  187. ~Get Your Files Here !/12. Verilog Design Examples/5.3 tb_encrypt.v 4KB
  188. ~Get Your Files Here !/11. Verilog State Machines/1. Discover Finite State Machines.srt 4KB
  189. ~Get Your Files Here !/4. Verilog Module/2. Action time - Do your first testbench.srt 4KB
  190. ~Get Your Files Here !/8. Verilog Sequential Design/12. Action Time - Shift_Reg_SIPO.srt 4KB
  191. ~Get Your Files Here !/8. Verilog Sequential Design/21. Action Time - Modulo_N Counter.srt 4KB
  192. ~Get Your Files Here !/4. Verilog Module/1. Verilog Module - the basics.srt 4KB
  193. ~Get Your Files Here !/7. Verilog Combinational Design/13. Action Time - 4to16 binary Decoder.srt 4KB
  194. ~Get Your Files Here !/11. Verilog State Machines/5. Action Time - Sequence Detector NON Overlaping.srt 4KB
  195. ~Get Your Files Here !/8. Verilog Sequential Design/2. Action Time - Clocks Generator.srt 4KB
  196. ~Get Your Files Here !/5. Verilog Design Styles/15. Action Time - 4bit_full_adder structural.srt 4KB
  197. ~Get Your Files Here !/5. Verilog Design Styles/6. Verilog_Behavioral_style.srt 4KB
  198. ~Get Your Files Here !/5. Verilog Design Styles/3. Action Time - half adder structural.srt 4KB
  199. ~Get Your Files Here !/11. Verilog State Machines/3.1 semaphore_fsm.v 4KB
  200. ~Get Your Files Here !/9. Verilog Functions and Tasks/7. Action Time - Nbit Comparator Function.srt 4KB
  201. ~Get Your Files Here !/2. Install the Simulator/3. Action Time - Hello World using Verilog.srt 4KB
  202. ~Get Your Files Here !/12. Verilog Design Examples/3.3 top_fsm.v 4KB
  203. ~Get Your Files Here !/8. Verilog Sequential Design/11. Action Time - Shift_Reg_PIPO.srt 4KB
  204. ~Get Your Files Here !/12. Verilog Design Examples/2.1 fifo_sync.v 4KB
  205. ~Get Your Files Here !/10. Verilog Memory Design/3.1 ram_sp_sync_read.v 3KB
  206. ~Get Your Files Here !/10. Verilog Memory Design/2.1 ram_sp_async_read.v 3KB
  207. ~Get Your Files Here !/7. Verilog Combinational Design/14. Action Time - 8to3 Encoder.srt 3KB
  208. ~Get Your Files Here !/7. Verilog Combinational Design/21. Action Time - demux_4x_nbit.srt 3KB
  209. ~Get Your Files Here !/11. Verilog State Machines/7. Verilog Mealy FSM Template.srt 3KB
  210. ~Get Your Files Here !/7. Verilog Combinational Design/25.1 ALU.v 3KB
  211. ~Get Your Files Here !/8. Verilog Sequential Design/6. Basics of edge-triggered logic.srt 3KB
  212. ~Get Your Files Here !/8. Verilog Sequential Design/19. Action Time - Nbit Counter.srt 3KB
  213. ~Get Your Files Here !/1. Introduction/4. Understand Abstraction Levels.srt 3KB
  214. ~Get Your Files Here !/8. Verilog Sequential Design/23. Action Time - Clock Divider Nbit.srt 3KB
  215. ~Get Your Files Here !/12. Verilog Design Examples/4. Basics of Data Ecryption.srt 3KB
  216. ~Get Your Files Here !/7. Verilog Combinational Design/8. Action Time - Nbit Adder.srt 3KB
  217. ~Get Your Files Here !/10. Verilog Memory Design/3. Action Time - Single Port Sync Read SRAM.srt 3KB
  218. ~Get Your Files Here !/7. Verilog Combinational Design/23. Action Time - HEX 7segment decoder.srt 3KB
  219. ~Get Your Files Here !/1. Introduction/5. Discover the Modern Digital Design Flow.srt 3KB
  220. ~Get Your Files Here !/7. Verilog Combinational Design/9. Action Time - Nbit Comparator.srt 3KB
  221. ~Get Your Files Here !/12. Verilog Design Examples/3.2 tb_top_fsm.v 3KB
  222. ~Get Your Files Here !/11. Verilog State Machines/2.1 fsm.v 3KB
  223. ~Get Your Files Here !/7. Verilog Combinational Design/11. Action Time - Nbit Decoder.srt 3KB
  224. ~Get Your Files Here !/6. Verilog Structural Design/13. Action Time - 1bit_comparator.srt 3KB
  225. ~Get Your Files Here !/5. Verilog Design Styles/15.1 ripple_adder_4bit_structural.v 3KB
  226. ~Get Your Files Here !/7. Verilog Combinational Design/19. Action Time - mux_4x_nbit.srt 3KB
  227. ~Get Your Files Here !/8. Verilog Sequential Design/1. Sequential Logic Basics.srt 3KB
  228. ~Get Your Files Here !/7. Verilog Combinational Design/4. Action Time - Adder Tree.srt 3KB
  229. ~Get Your Files Here !/7. Verilog Combinational Design/22. Master the Seven Segment Display Decoder.srt 3KB
  230. ~Get Your Files Here !/8. Verilog Sequential Design/13. Action Time - Shift_Reg_SISO.srt 3KB
  231. ~Get Your Files Here !/6. Verilog Structural Design/5. Action Time - 1bit_mux.srt 3KB
  232. ~Get Your Files Here !/6. Verilog Structural Design/7. Action Time -1bit_demux.srt 3KB
  233. ~Get Your Files Here !/3. Verilog Data Types and Operators/8. Action time - Vectors.srt 3KB
  234. ~Get Your Files Here !/5. Verilog Design Styles/16.1 ripple_adder_4bit_dataflow.v 3KB
  235. ~Get Your Files Here !/5. Verilog Design Styles/5. Action Time - half_adder dataflow.srt 3KB
  236. ~Get Your Files Here !/10. Verilog Memory Design/1. Basics of Semiconductor Memory.srt 3KB
  237. ~Get Your Files Here !/9. Verilog Functions and Tasks/13. Discover Automated Verification.srt 2KB
  238. ~Get Your Files Here !/5. Verilog Design Styles/11. Action Time - full_adder structural.srt 2KB
  239. ~Get Your Files Here !/9. Verilog Functions and Tasks/12.1 shift_reg_pipo_buggy.v 2KB
  240. ~Get Your Files Here !/7. Verilog Combinational Design/16. Action Time - Priority Encoder1 4to2.srt 2KB
  241. ~Get Your Files Here !/9. Verilog Functions and Tasks/10. Action Time - Verilog Tasks Control Shift Reg.srt 2KB
  242. ~Get Your Files Here !/7. Verilog Combinational Design/24. How to use digital logic for arithmetic operations.srt 2KB
  243. ~Get Your Files Here !/6. Verilog Structural Design/11. Action Time - mux_tri-state.srt 2KB
  244. ~Get Your Files Here !/6. Verilog Structural Design/4. Discover the Multiplexer.srt 2KB
  245. ~Get Your Files Here !/3. Verilog Data Types and Operators/2. Action time - sum and product.srt 2KB
  246. ~Get Your Files Here !/3. Verilog Data Types and Operators/4. Action time - Multiple procedures.srt 2KB
  247. ~Get Your Files Here !/8. Verilog Sequential Design/4. Action Time - The D_Latch.srt 2KB
  248. ~Get Your Files Here !/11. Verilog State Machines/6.1 seq_det_overlap.v 2KB
  249. ~Get Your Files Here !/12. Verilog Design Examples/1. Discover the First In First Out (FIFO) circuit.srt 2KB
  250. ~Get Your Files Here !/8. Verilog Sequential Design/10. Discover the Shift Register.srt 2KB
  251. ~Get Your Files Here !/8. Verilog Sequential Design/5. Action Time - D_Latch_reset_n.srt 2KB
  252. ~Get Your Files Here !/11. Verilog State Machines/5.1 seq_det_non_overlap.v 2KB
  253. ~Get Your Files Here !/7. Verilog Combinational Design/6. Action Time - Tree Adder Procedural.srt 2KB
  254. ~Get Your Files Here !/5. Verilog Design Styles/16. Action Time - 4bit_full_adder dataflow.srt 2KB
  255. ~Get Your Files Here !/8. Verilog Sequential Design/18. Discover Synchronous Counters.srt 2KB
  256. ~Get Your Files Here !/7. Verilog Combinational Design/3. Action Time - Continuous assignments.srt 2KB
  257. ~Get Your Files Here !/5. Verilog Design Styles/13. Action Time - full_adder behavioral.srt 2KB
  258. ~Get Your Files Here !/9. Verilog Functions and Tasks/5. Action Time - Verilog Functions Factorial.srt 2KB
  259. ~Get Your Files Here !/7. Verilog Combinational Design/17. Action Time - Priority Encoder2 4to2.srt 2KB
  260. ~Get Your Files Here !/9. Verilog Functions and Tasks/1. Verilog Functions Basics.srt 2KB
  261. ~Get Your Files Here !/8. Verilog Sequential Design/3. Types of Sequential Digital Logic.srt 2KB
  262. ~Get Your Files Here !/8. Verilog Sequential Design/15.1 shift_left_right_load_reg.v 2KB
  263. ~Get Your Files Here !/8. Verilog Sequential Design/20.1 counter_up_down_load_nbit.v 2KB
  264. ~Get Your Files Here !/3. Verilog Data Types and Operators/6. Action time - Literal values.srt 2KB
  265. ~Get Your Files Here !/6. Verilog Structural Design/2. Verilog Built-in_Primitives.srt 2KB
  266. ~Get Your Files Here !/8. Verilog Sequential Design/22. Discover Digital Frequency Dividers.srt 2KB
  267. ~Get Your Files Here !/7. Verilog Combinational Design/1. What is Combinational logic.srt 2KB
  268. ~Get Your Files Here !/8. Verilog Sequential Design/24.1 clock_div_3.v 2KB
  269. ~Get Your Files Here !/6. Verilog Structural Design/6. Discover the Demultiplexer.srt 2KB
  270. ~Get Your Files Here !/3. Verilog Data Types and Operators/10. Action Time - Bit-wise operators.srt 2KB
  271. ~Get Your Files Here !/7. Verilog Combinational Design/15. What is a Priority Encoder.srt 2KB
  272. ~Get Your Files Here !/8. Verilog Sequential Design/8. Action Time - D_Flip_Flop_async_rstn.srt 2KB
  273. ~Get Your Files Here !/9. Verilog Functions and Tasks/10.1 task_control_shift_reg.v 2KB
  274. ~Get Your Files Here !/2. Install the Simulator/2. Install Intel Quartus Prime Lite and Modelsim.srt 2KB
  275. ~Get Your Files Here !/9. Verilog Functions and Tasks/2. Action Time - Verilog Functions1.srt 2KB
  276. ~Get Your Files Here !/7. Verilog Combinational Design/5. Discover Procedural Assignments.srt 2KB
  277. ~Get Your Files Here !/4. Verilog Module/6. Action Time - Generate Waveforms.srt 2KB
  278. ~Get Your Files Here !/8. Verilog Sequential Design/23.1 clock_div_nbit.v 2KB
  279. ~Get Your Files Here !/3. Verilog Data Types and Operators/29. Action Time - Replication Operator.srt 2KB
  280. ~Get Your Files Here !/3. Verilog Data Types and Operators/15. Action Time - Logical Operators usage.srt 2KB
  281. ~Get Your Files Here !/3. Verilog Data Types and Operators/15.1 logical_operators_usage.v 2KB
  282. ~Get Your Files Here !/8. Verilog Sequential Design/16. Discover the Linear Feedback Shift Register.srt 2KB
  283. ~Get Your Files Here !/5. Verilog Design Styles/11.1 full_adder_structural.v 2KB
  284. ~Get Your Files Here !/7. Verilog Combinational Design/13.1 decoder_4to16.v 2KB
  285. ~Get Your Files Here !/7. Verilog Combinational Design/10. Differentiate between binary encoders and decoders.srt 2KB
  286. ~Get Your Files Here !/3. Verilog Data Types and Operators/12. Action Time - Reduction operators.srt 2KB
  287. ~Get Your Files Here !/3. Verilog Data Types and Operators/27. Action Time - Concatenation Operator.srt 2KB
  288. ~Get Your Files Here !/7. Verilog Combinational Design/23.1 hex_7seg_decoder.v 2KB
  289. ~Get Your Files Here !/5. Verilog Design Styles/8. Action Time - Initial Procedures.srt 2KB
  290. ~Get Your Files Here !/6. Verilog Structural Design/9. Action Time - tri-state_buffer.srt 2KB
  291. ~Get Your Files Here !/9. Verilog Functions and Tasks/4. Discover Verilog Recursive Functions.srt 2KB
  292. ~Get Your Files Here !/5. Verilog Design Styles/10. Design a 1bit full_adder.srt 2KB
  293. ~Get Your Files Here !/1. Introduction/3. What is Verilog HDL.srt 2KB
  294. ~Get Your Files Here !/10. Verilog Memory Design/5.2 rom.v 2KB
  295. ~Get Your Files Here !/3. Verilog Data Types and Operators/3. Hardware Description Language data types.srt 2KB
  296. ~Get Your Files Here !/3. Verilog Data Types and Operators/9. Verilog Operators - Bit-wise.srt 2KB
  297. ~Get Your Files Here !/5. Verilog Design Styles/9. Action Time - half_adder behavioral.srt 2KB
  298. ~Get Your Files Here !/8. Verilog Sequential Design/14.1 shift_reg_piso.v 2KB
  299. ~Get Your Files Here !/11. Verilog State Machines/6. Action Time - Sequence Detector Overlaping.srt 2KB
  300. ~Get Your Files Here !/5. Verilog Design Styles/12. Action Time - full_adder dataflow.srt 2KB
  301. ~Get Your Files Here !/9. Verilog Functions and Tasks/7.1 compare_nbit_func.v 2KB
  302. ~Get Your Files Here !/7. Verilog Combinational Design/18. Discover bus Multiplexers.srt 2KB
  303. ~Get Your Files Here !/3. Verilog Data Types and Operators/1. Verilog Data types overview.srt 1KB
  304. ~Get Your Files Here !/8. Verilog Sequential Design/21.1 counter_modulo_n.v 1KB
  305. ~Get Your Files Here !/3. Verilog Data Types and Operators/19. Action Time - Shift Operators.srt 1KB
  306. ~Get Your Files Here !/8. Verilog Sequential Design/12.1 shift_reg_sipo.v 1KB
  307. ~Get Your Files Here !/2. Install the Simulator/1. Discover the Verilog Simulation.srt 1KB
  308. ~Get Your Files Here !/5. Verilog Design Styles/17. Action Time - 4bit_full_adder behavioral.srt 1KB
  309. ~Get Your Files Here !/3. Verilog Data Types and Operators/31. Action Time - Operators Precedence.srt 1KB
  310. ~Get Your Files Here !/7. Verilog Combinational Design/6.1 adders3_procedural.v 1KB
  311. ~Get Your Files Here !/9. Verilog Functions and Tasks/11. Why our code looks like software.srt 1KB
  312. ~Get Your Files Here !/9. Verilog Functions and Tasks/9. Action Time - Verilog Tasks Distance Conversion.srt 1KB
  313. ~Get Your Files Here !/8. Verilog Sequential Design/13.1 shift_reg_siso.v 1KB
  314. ~Get Your Files Here !/7. Verilog Combinational Design/19.1 mux_4x_nbit.v 1KB
  315. ~Get Your Files Here !/7. Verilog Combinational Design/21.1 demux_nbit_x4.v 1KB
  316. ~Get Your Files Here !/9. Verilog Functions and Tasks/6. Action Time - Verilog Functions Fibonacci.srt 1KB
  317. ~Get Your Files Here !/5. Verilog Design Styles/12.1 full_adder_dataflow.v 1KB
  318. ~Get Your Files Here !/3. Verilog Data Types and Operators/21. Action Time - Relational Operators.srt 1KB
  319. ~Get Your Files Here !/8. Verilog Sequential Design/8.1 d_ff_async_rstn.v 1KB
  320. ~Get Your Files Here !/8. Verilog Sequential Design/7.1 d_ff_sync_rstn.v 1KB
  321. ~Get Your Files Here !/3. Verilog Data Types and Operators/25. Action Time - Conditional Operator.srt 1KB
  322. ~Get Your Files Here !/9. Verilog Functions and Tasks/3. Action Time - Verilog Functions2.srt 1KB
  323. ~Get Your Files Here !/7. Verilog Combinational Design/20. Discover bus Demultiplexers.srt 1KB
  324. ~Get Your Files Here !/5. Verilog Design Styles/2. Verilog Structural Design.srt 1KB
  325. ~Get Your Files Here !/8. Verilog Sequential Design/17.1 lfsr_16.v 1KB
  326. ~Get Your Files Here !/3. Verilog Data Types and Operators/17.1 math_operators.v 1KB
  327. ~Get Your Files Here !/4. Verilog Module/4. What is a Testbench Architecture.srt 1KB
  328. ~Get Your Files Here !/7. Verilog Combinational Design/9.1 comparator_nbit.v 1KB
  329. ~Get Your Files Here !/4. Verilog Module/5. Discover Time and Waveforms.srt 1KB
  330. ~Get Your Files Here !/3. Verilog Data Types and Operators/14. Action Time - Logical Operators.srt 1KB
  331. ~Get Your Files Here !/3. Verilog Data Types and Operators/31.1 operators_precedence.v 1KB
  332. ~Get Your Files Here !/6. Verilog Structural Design/3. Action Time - Built-in_gates.srt 1KB
  333. ~Get Your Files Here !/3. Verilog Data Types and Operators/14.1 logical_operators.v 1KB
  334. ~Get Your Files Here !/8. Verilog Sequential Design/5.1 d_latch_rstn.v 1KB
  335. ~Get Your Files Here !/5. Verilog Design Styles/14. Design a 4bit full_adder.srt 1KB
  336. ~Get Your Files Here !/8. Verilog Sequential Design/19.1 counter_nbit.v 1KB
  337. ~Get Your Files Here !/5. Verilog Design Styles/17.1 adder_4bit_behavioral.v 1KB
  338. ~Get Your Files Here !/2. Install the Simulator/4. Congratulations!.srt 1KB
  339. ~Get Your Files Here !/3. Verilog Data Types and Operators/10.1 bitwise_operators.v 1KB
  340. ~Get Your Files Here !/3. Verilog Data Types and Operators/5. What are Literal Values.srt 1KB
  341. ~Get Your Files Here !/5. Verilog Design Styles/1. What are HDL Design Styles.srt 1KB
  342. ~Get Your Files Here !/12. Verilog Design Examples/5.4 top_encrypt_golden.v 1KB
  343. ~Get Your Files Here !/6. Verilog Structural Design/10. How to implement a multiplexer using tri-state buffers.srt 1KB
  344. ~Get Your Files Here !/3. Verilog Data Types and Operators/23.1 equality_operators.v 1KB
  345. ~Get Your Files Here !/7. Verilog Combinational Design/16.1 prio_enc1_4to2.v 1KB
  346. ~Get Your Files Here !/3. Verilog Data Types and Operators/22. Verilog Operators - Equality.srt 1KB
  347. ~Get Your Files Here !/9. Verilog Functions and Tasks/8. Verilog Tasks Basics.srt 1KB
  348. ~Get Your Files Here !/3. Verilog Data Types and Operators/18. Verilog Operators - Shift.srt 1KB
  349. ~Get Your Files Here !/7. Verilog Combinational Design/2. Discover Continuous assignments.srt 1KB
  350. ~Get Your Files Here !/12. Verilog Design Examples/6. Congratulations!.srt 1KB
  351. ~Get Your Files Here !/11. Verilog State Machines/4. Basics of Sequence Detectors.srt 1KB
  352. ~Get Your Files Here !/5. Verilog Design Styles/8.1 procedures.v 1KB
  353. ~Get Your Files Here !/7. Verilog Combinational Design/4.1 adders3.v 1KB
  354. ~Get Your Files Here !/3. Verilog Data Types and Operators/12.1 reduction_operators.v 1KB
  355. ~Get Your Files Here !/7. Verilog Combinational Design/12. How to use multiple binary decoders.srt 1KB
  356. ~Get Your Files Here !/3. Verilog Data Types and Operators/8.1 easy_vectors_example.v 1KB
  357. ~Get Your Files Here !/6. Verilog Structural Design/8. The Tri-state buffer.srt 1KB
  358. ~Get Your Files Here !/8. Verilog Sequential Design/9. Remember!.srt 1KB
  359. ~Get Your Files Here !/8. Verilog Sequential Design/4.1 d_latch.v 1KB
  360. ~Get Your Files Here !/3. Verilog Data Types and Operators/7. Vectors in Verilog.srt 1KB
  361. ~Get Your Files Here !/3. Verilog Data Types and Operators/28. Verilog Operators - Replication.srt 1023B
  362. ~Get Your Files Here !/3. Verilog Data Types and Operators/27.1 concatention_operator.v 1015B
  363. ~Get Your Files Here !/6. Verilog Structural Design/1. What is Structural Design.srt 1012B
  364. ~Get Your Files Here !/7. Verilog Combinational Design/8.1 adder_nbit.v 1004B
  365. ~Get Your Files Here !/12. Verilog Design Examples/5.5 top_encrypt.v 990B
  366. ~Get Your Files Here !/7. Verilog Combinational Design/11.1 decoder_nbit.v 968B
  367. ~Get Your Files Here !/3. Verilog Data Types and Operators/17. Action Time - Arithmetic Operators.srt 948B
  368. ~Get Your Files Here !/5. Verilog Design Styles/3.1 half_adder_structural.v 946B
  369. ~Get Your Files Here !/3. Verilog Data Types and Operators/6.1 literal_values.v 940B
  370. ~Get Your Files Here !/6. Verilog Structural Design/13.1 comparator_1bit.v 936B
  371. ~Get Your Files Here !/3. Verilog Data Types and Operators/13. Verilog Operators - Logical.srt 933B
  372. ~Get Your Files Here !/5. Verilog Design Styles/9.1 half_adder_behavioral.v 928B
  373. ~Get Your Files Here !/11. Verilog State Machines/7.1 fsm_template.v 911B
  374. ~Get Your Files Here !/5. Verilog Design Styles/5.1 half_adder_dataflow.v 906B
  375. ~Get Your Files Here !/5. Verilog Design Styles/18. Congratulations!.srt 866B
  376. ~Get Your Files Here !/8. Verilog Sequential Design/2.1 clkgen.v 857B
  377. ~Get Your Files Here !/3. Verilog Data Types and Operators/19.1 shift_operators.v 829B
  378. ~Get Your Files Here !/3. Verilog Data Types and Operators/29.1 replication_operator.v 828B
  379. ~Get Your Files Here !/9. Verilog Functions and Tasks/9.1 task_meters_to_feet.v 806B
  380. ~Get Your Files Here !/5. Verilog Design Styles/4. Verilog Dataflow style.srt 799B
  381. ~Get Your Files Here !/3. Verilog Data Types and Operators/11. Verilog Operators - Reduction.srt 784B
  382. ~Get Your Files Here !/6. Verilog Structural Design/11.1 mux_tristate.v 784B
  383. ~Get Your Files Here !/3. Verilog Data Types and Operators/23. Action Time - Equality Operators.srt 768B
  384. ~Get Your Files Here !/7. Verilog Combinational Design/7. Discover the Nbit Adder.srt 767B
  385. ~Get Your Files Here !/6. Verilog Structural Design/12. Discover the 1bit Comparator.srt 766B
  386. ~Get Your Files Here !/7. Verilog Combinational Design/3.1 some_logic.v 762B
  387. ~Get Your Files Here !/4. Verilog Module/2.2 my_first_testbench.v 758B
  388. ~Get Your Files Here !/6. Verilog Structural Design/14. Remember!.srt 728B
  389. ~Get Your Files Here !/3. Verilog Data Types and Operators/32. Congratulations!.srt 714B
  390. ~Get Your Files Here !/3. Verilog Data Types and Operators/30. Verilog Operators - Precedence.srt 709B
  391. ~Get Your Files Here !/3. Verilog Data Types and Operators/26. Verilog Operators - Concatenation.srt 704B
  392. ~Get Your Files Here !/9. Verilog Functions and Tasks/6.1 function_ex4.v 688B
  393. ~Get Your Files Here !/3. Verilog Data Types and Operators/24. Verilog Operators - Conditional.srt 671B
  394. ~Get Your Files Here !/4. Verilog Module/3. Remember!.srt 667B
  395. ~Get Your Files Here !/6. Verilog Structural Design/3.1 built_in_gates.v 667B
  396. ~Get Your Files Here !/6. Verilog Structural Design/3.2 tb_gates.v 661B
  397. ~Get Your Files Here !/3. Verilog Data Types and Operators/25.1 conditional_operators.v 648B
  398. ~Get Your Files Here !/9. Verilog Functions and Tasks/5.1 function_ex3.v 633B
  399. ~Get Your Files Here !/7. Verilog Combinational Design/26. Remember!.srt 628B
  400. ~Get Your Files Here !/5. Verilog Design Styles/7. Remember!.srt 626B
  401. ~Get Your Files Here !/6. Verilog Structural Design/7.2 tb_demux.v 623B
  402. ~Get Your Files Here !/3. Verilog Data Types and Operators/20. Verilog Operators - Relational.srt 618B
  403. ~Get Your Files Here !/12. Verilog Design Examples/3.1 ram_dp_async_read.v 609B
  404. ~Get Your Files Here !/9. Verilog Functions and Tasks/2.1 function_ex1.v 588B
  405. ~Get Your Files Here !/12. Verilog Design Examples/5.1 prng.v 570B
  406. ~Get Your Files Here !/9. Verilog Functions and Tasks/3.1 function_ex2.v 557B
  407. ~Get Your Files Here !/6. Verilog Structural Design/9.1 tb_tristate.v 539B
  408. ~Get Your Files Here !/3. Verilog Data Types and Operators/21.1 relational_operators.v 507B
  409. ~Get Your Files Here !/6. Verilog Structural Design/5.2 tb_mux.v 506B
  410. ~Get Your Files Here !/3. Verilog Data Types and Operators/2.1 sum_product.v 433B
  411. ~Get Your Files Here !/4. Verilog Module/6.1 waveforms.v 425B
  412. ~Get Your Files Here !/3. Verilog Data Types and Operators/16. Verilog Operators - Arithmetic.srt 413B
  413. ~Get Your Files Here !/Bonus Resources.txt 357B
  414. ~Get Your Files Here !/6. Verilog Structural Design/5.1 mux_1bit.v 271B
  415. ~Get Your Files Here !/6. Verilog Structural Design/7.1 demux_1bit.v 224B
  416. ~Get Your Files Here !/2. Install the Simulator/3.1 hello_world.v 208B
  417. Get Bonus Downloads Here.url 180B
  418. ~Get Your Files Here !/6. Verilog Structural Design/9.2 tristate_buffer_1bit.v 137B
  419. ~Get Your Files Here !/4. Verilog Module/2.1 adder8bit.v 133B
  420. ~Get Your Files Here !/12. Verilog Design Examples/5.2 secret_message.txt 110B
  421. ~Get Your Files Here !/10. Verilog Memory Design/5.1 rom_init.hex 66B